LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 356
LPC2460FET208,551
Manufacturer Part Number
LPC2460FET208,551
Description
IC ARM7 MCU ROMLESS 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2460FET208,551
Program Memory Type
ROMless
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4260
935283232551
LPC2460FET208-S
935283232551
LPC2460FET208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2460FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
9.8.6 USB EP DMA Enable register (USBEpDMAEn - 0xFFE0 C288)
9.8.7 USB EP DMA Disable register (USBEpDMADis - 0xFFE0 C28C)
9.8.8 USB DMA Interrupt Status register (USBDMAIntSt - 0xFFE0 C290)
Writing one to a bit to this register will enable the DMA operation for the corresponding
endpoint. Writing zero has no effect.The DMA cannot be enabled for control endpoints
EP0 and EP1. USBEpDMAEn is a write only register.
Table 334. USB EP DMA Enable register (USBEpDMAEn - address 0xFFE0 C288) bit
Writing a one to a bit in this register clears the corresponding bit in USBEpDMASt. Writing
zero has no effect on the corresponding bit of USBEpDMASt. Any write to this register
clears the internal DMA_PROCEED flag. Refer to
descriptor fetch”
progress for an endpoint when its corresponding bit is cleared, the transfer is completed
before the DMA is disabled. When an error condition is detected during a DMA transfer,
the corresponding bit is cleared by hardware. USBEpDMADis is a write only register.
Table 335. USB EP DMA Disable register (USBEpDMADis - address 0xFFE0 C28C) bit
Each bit of this register reflects whether any of the 32 bits in the corresponding interrupt
status register are set. USBDMAIntSt is a read only register.
Bit
0
1
31:2 EPxx_DMA_ENABLE
Bit
0
1
31:2 EPxx_DMA_DISABLE
Symbol
EP0_DMA_ENABLE
EP1_DMA_ENABLE
Symbol
EP0_DMA_DISABLE
EP1_DMA_DISABLE
description
description
for more information on the DMA_PROCEED flag. If a DMA transfer is in
Rev. 04 — 26 August 2009
Value Description
0
0
0
1
Value Description
0
0
0
1
Control endpoint OUT (DMA cannot be enabled for
this endpoint and the EP0_DMA_ENABLE bit value
must be 0).
Control endpoint IN (DMA cannot be enabled for this
endpoint and the EP1_DMA_ENABLE bit must be 0).
Endpoint xx(2 ≤ xx ≤ 31) DMA enable control bit.
No effect.
Enable the DMA operation for endpoint EPxx.
Control endpoint OUT (DMA cannot be enabled for
this endpoint and the EP0_DMA_DISABLE bit value
must be 0).
Control endpoint IN (DMA cannot be enabled for
this endpoint and the EP1_DMA_DISABLE bit value
must be 0).
Endpoint xx (2 ≤ xx ≤ 31) DMA disable control bit.
No effect.
Disable the DMA operation for endpoint EPxx.
Chapter 13: LPC24XX USB device controller
Section 13–14.5.4 “Optimizing
UM10237
© NXP B.V. 2009. All rights reserved.
356 of 792
Reset
value
0
0
0
Reset
value
0
0
0
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