LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 576
LPC2460FET208,551
Manufacturer Part Number
LPC2460FET208,551
Description
IC ARM7 MCU ROMLESS 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2460FET208,551
Program Memory Type
ROMless
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4260
935283232551
LPC2460FET208-S
935283232551
LPC2460FET208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2460FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
6.3 Slave Receiver mode
In the slave receiver mode, data bytes are received from a master transmitter. To initialize
the slave receiver mode, user write the Slave Address Register (I2ADR) and write the I
Control Set Register (I2CONSET) as shown in
Table 511. I2CnCONSET used to configure Slave mode
I2EN must be set to 1 to enable the I
its own slave address or the general call address. The STA, STO and SI bits are set to 0.
After I2ADR and I2CONSET are initialized, the I
its own address or general address followed by the data direction bit. If the direction bit is
0 (W), it enters slave receiver mode. If the direction bit is 1 (R), it enters slave transmitter
mode. After the address and direction bit have been received, the SI bit is set and a valid
status code can be read from the Status Register (I2STAT). Refer to
status codes and actions.
Bit
Symbol
Value
Fig 114. A master receiver switch to master Transmitter after sending repeated START
Fig 115. Format of Slave Receiver mode
S
S
from Master to Slave
from Slave to Master
From master to slave
From slave to master
SLA
SLAVE ADDRESS
7
-
-
R
A
6
I2EN
1
Rev. 04 — 26 August 2009
DATA
“0” - write
“1” - read
(n Bytes + Acknowledge)
W
data transferred
5
STA
0
A
2
DATA
A
C function. AA bit must be set to 1 to acknowledge
4
STO
0
Chapter 22: LPC24XX I
A
DATA
Table
2
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
P = STOP condition
RS = Repeated START condition
RS
C interface waits until it is addressed by
3
SI
0
(n Bytes + Acknowledge)
22–511.
SLA
data transferred
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
P = STOP condition
SLA = Slave Address
A
2
AA
1
W
DATA
A
2
C interfaces I
Table 22–527
UM10237
1
-
-
© NXP B.V. 2009. All rights reserved.
DATA
A/A
A
0
-
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576 of 792
2
for the
C0/1/2
P/RS
P
2
C
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