EP9312-IB Cirrus Logic Inc, EP9312-IB Datasheet - Page 565
EP9312-IB
Manufacturer Part Number
EP9312-IB
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(824 pages)
2.EP9312-IBZ.pdf
(4 pages)
3.EP9312-CB.pdf
(62 pages)
4.EP9312-CB.pdf
(17 pages)
Specifications of EP9312-IB
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
352-BGA
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1259
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9312-IBZ
Manufacturer:
CIRRUS
Quantity:
30
Company:
Part Number:
EP9312-IBZ
Manufacturer:
HITTITE
Quantity:
1 200
- EP9307-CRZ PDF datasheet
- EP9312-IBZ PDF datasheet #2
- EP9312-CB PDF datasheet #3
- EP9312-CB PDF datasheet #4
- Current page: 565 of 824
- Download datasheet (13Mb)
Register Descriptions
UART2Data
DS785UM1
15.4 Registers
31
15
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
0x808D_0000 - Read/Write
0x0000_0000
UART Data Register
RSVD:
DATA:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
UART Data, read for receive data, write for transmit data
For words to be transmitted:
• if the FIFOs are enabled, data written to this location is
pushed onto the transmit FIFO
• if the FIFOs are not enabled, data is stored in the
transmitter holding register (the bottom word of the
transmit FIFO). The write operation initiates transmission
from the UART. The data is prefixed with a start bit,
appended with the appropriate parity bit (if parity is
enabled), and a stop bit. The resultant word is then
transmitted.
For received words:
• if the FIFOs are enabled, the data byte is extracted, and
a 3-bit status (break, frame and parity) is pushed onto the
11-bit wide receive FIFO
• if the FIFOs are not enabled, the data byte and status are
stored in the receiving holding register (the bottom word of
the receive FIFO).
24
8
RSVD
23
7
22
6
21
5
20
4
DATA
19
3
EP93xx User’s Guide
18
2
17
1
UART2
16
15-7
0
15
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