ST72F561J4T6 STMicroelectronics, ST72F561J4T6 Datasheet - Page 244

• Manufacturer Part Number: ST72F561J4T6
• Description: IC MCU 8BIT 16K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F561J4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: ST72F5x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: 497-8374 - BOARD DEVELOPMENT FOR ST72F561
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST72561
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
Figure 139. SPI Slave Timing Diagram with CPHA = 1
Figure 140. SPI Master Timing Diagram
Notes:
1. Measurement points are done at CMOS levels: 0.3 x V
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
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MISO
MOSI
MISO
MOSI
SS
CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
SS
OUTPUT
INPUT
CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
CPHA = 1
CPOL = 0
CPHA = 1
CPOL = 1
INPUT
INPUT
OUTPUT
INPUT
See
note 2
See note 2
t
a(SO)
t
su(SS)
Hz
t
t
t
v(MO)
t
w(SCKH)
w(SCKL)
su(MI)
t
su(SI)
MSB OUT
MSB IN
MSB OUT
t
h(MO)
t
MSB IN
h(MI)
t
h(SI)
1)
t
c(SCK)
t
c(SCK)
t
t
t
v(SO)
w(SCKH)
w(SCKL)
DD
BIT6 OUT
and 0.7 x V
BIT6 OUT
BIT6 IN
1)
DD
BIT1 IN
.
t
h(SO)
t
t
t
t
r(SCK)
f(SCK)
r(SCK)
f(SCK)
LSB OUT
LSB IN
LSB OUT
LSB IN
t
h(SS)
t
See note 2
dis(SO)
See
note 2