F272-BAG-T-TR STMicroelectronics, F272-BAG-T-TR Datasheet - Page 151

• Manufacturer Part Number: F272-BAG-T-TR
• Description: MCU 16BIT 256K FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of F272-BAG-T-TR

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: ASC, CAN, I2C, SSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

ST10F272B/ST10F272E
Table 69.
24.8.9
0
0
0
(P0H.7-5)
P0.15-13
1
0
0
0
1
0
Internal PLL divider mechanism (continued)
The PLL input frequency range is limited to 1 to 3.5MHz, while the VCO oscillation range is
64 to 128MHz. The CPU clock frequency range when PLL is used is 16 to 64MHz.
Example 1
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Example 2
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PLL Jitter
The following terminology is hereafter defined:
●
●
Jitter at the PLL output can be due to the following reasons:
●
●
4 to 12MHz
4 to 6.4MHz
Frequency
F
P0(15:13) = ‘110’ (Multiplication by 3)
PLL Input Frequency = 1MHz
VCO frequency = 48MHz
PLL Output Frequency = 12MHz
(VCO frequency divided by 4)
F
F
P0(15:13) = ‘100’ (Multiplication by 5)
PLL Input Frequency = 2MHz
VCO frequency = 80MHz
PLL Output Frequency = 40MHz (VCO frequency divided by 2)
F
Self referred single period jitter
Also called “Period Jitter”, it can be defined as the difference of the T
where T
time period of the PLL output clock.
Self referred long term jitter
Also called “N period jitter”, it can be defined as the difference of T
T
minimum time difference between N+1 clock rising edges. Here N should be kept
sufficiently large to have the long term jitter. For N=1, this becomes the single period
jitter.
Jitter in the input clock
Noise in the PLL loop.
XTAL
CPU
XTAL
CPU
max
4MHz
XTAL
is the maximum time difference between N+1 clock rising edges and T
= 12MHz (no effect of Output Prescaler)
= 40MHz (no effect of Output Prescaler)
= 4MHz
= 8MHz
max
1)
is maximum time period of the PLL output clock and T
Prescaler
F
F
XTAL
XTAL
Input
–
/ 2
/ 2
Multiply by
40
64
PLL bypassed
PLL
Divide by
2
2
Prescaler
F
Output
PLL
–
–
Electrical characteristics
/ 2
max
min
max
CPU Frequency
f
is the minimum
and T
CPU
F
F
and T
F
XTAL
XTAL
= f
XTAL
min
min
XTAL
x 10
x 16
min
/ 2
, where
is the
151/182
x F
,