F272-BAG-T-TR STMicroelectronics, F272-BAG-T-TR Datasheet - Page 28

• Manufacturer Part Number: F272-BAG-T-TR
• Description: MCU 16BIT 256K FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of F272-BAG-T-TR

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: ASC, CAN, I2C, SSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Internal Flash memory
5.2.2
28/182
Modules structure
The IFLASH module is composed by a bank (Bank 0) of 256 Kbyte of Program Memory
divided in 8 sectors (B0F0...B0F7). Bank 0 contains also a reserved sector named Test-
Flash. The Addresses from 0x08 0000 to 0x08 FFFF are reserved for the Control Register
Interface and other internal service memory space used by the Flash Program/Erase
controller.
The following tables show the memory mapping of the Flash when it is accessed in read
mode
write or erase mode
ROMS1=’1’ or BootStrap
are remapped into code segment 1 (same as obtained setting bit ROMS1 in SYSCON
register).
Table 4.
Table 5.
The table above refers to the configuration when bit ROMS1 of SYSCON register is set.
Bank
Bank
B0
B0
(Table 4: Flash modules sectorization (Read
Flash modules sectorization (Read operations)
Flash modules sectorization
(Write operations or with ROMS1=’1’ or BootStrap mode)
Bank 0 Test-Flash (B0TF)
Bank 0 Flash 0 (B0F0)
Bank 0 Flash 1 (B0F1)
Bank 0 Flash 2 (B0F2)
Bank 0 Flash 3 (B0F3)
Bank 0 Flash 4 (B0F4)
Bank 0 Flash 5 (B0F5)
Bank 0 Flash 6 (B0F6)
Bank 0 Flash 7 (B0F7)
Bank 0 Flash 0 (B0F0)
Bank 0 Flash 1 (B0F1)
Bank 0 Flash 2 (B0F2)
Bank 0 Flash 3 (B0F3)
Bank 0 Flash 4 (B0F4)
Bank 0 Flash 5 (B0F5)
Bank 0 Flash 6 (B0F6)
Bank 0 Flash 7 (B0F7)
Description
Description
(Table 5: Flash modules sectorization (Write operations or with
mode)): note that with this second mapping, the first four banks
0x0001 8000 - 0x0001 FFFF
0x0002 0000 - 0x0002 FFFF
0x0003 0000 - 0x0003 FFFF
0x0004 0000 - 0x0004 FFFF
0x0000 0000 - 0x0000 1FFF
0x0000 2000 - 0x0000 3FFF
0x0000 4000 - 0x0000 5FFF
0x0000 6000 - 0x0000 7FFF
0x0000 0000 - 0x0000 1FFF
0x0001 0000 - 0x0001 1FFF
0x0001 2000 - 0x0001 3FFF
0x0001 4000 - 0x0001 5FFF
0x0001 6000 - 0x0001 7FFF
0x0001 8000 - 0x0001 FFFF 32 KB
0x0002 0000 - 0x0002 FFFF 64 KB
0x0003 0000 - 0x0003 FFFF 64 KB
0x0004 0000 - 0x0004 FFFF 64 KB
Addresses
Addresses
operations)), and when accessed in
ST10F272B/ST10F272E
32 KB
64 KB
64 KB
64 KB
8 KB
8 KB
8 KB
8 KB
Size
8 KB
8 KB
8 KB
8 KB
8 KB
Size
ST10 Bus size
ST10 Bus size
32-bit (I-BUS)
32-bit (I-BUS)