F272-BAG-T-TR STMicroelectronics, F272-BAG-T-TR Datasheet - Page 157

• Manufacturer Part Number: F272-BAG-T-TR
• Description: MCU 16BIT 256K FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of F272-BAG-T-TR

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: ASC, CAN, I2C, SSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

ST10F272B/ST10F272E
Note:
24.8.14
24.8.15
Note:
Figure 49. External clock drive XTAL1
When Direct Drive is selected, an external clock source can be used to drive XTAL1. The
maximum frequency of the external clock source depends on the duty cycle: when 64MHz is
used, 50% duty cycle shall be granted (low phase = high phase = 7.8ns); when for instance
32MHz is used, a 25% duty cycle can be accepted (minimum phase, high or low, again
equal to 7.8ns).
Memory cycle variables
The tables below use three variables which are derived from the BUSCONx registers and
represent the special characteristics of the programmed memory cycle. The following table
describes, how these variables are to be computed.
Table 76.
External memory bus timing
The following sections include the External Memory Bus timings. The given values are
computed for a maximum CPU clock of 40MHz.
Obviously, when higher CPU clock frequency is used (up to 64MHz), some numbers in the
timing formulas become zero or negative which, in most cases is not acceptable or not
meaningless at all. In these cases, it is necessary to relax the speed of the bus setting
properly t
All External Memory Bus Timings and SSC Timings reported in the following tables are
granted by Design Characterization and not fully tested in production.
ALE Extension
Memory Cycle Time wait states
Memory Tri-state Time
A
, t
Description
C
Memory cycle variables
and t
F
.
t1
VIH2
Symbol
t
t
t
C
A
F
t2
t3
TCL x [ALECTL]
2TCL x (15 - [MCTC])
2TCL x (1 - [MTTC])
t
VIL2
OSC
Electrical characteristics
Values
t4
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