F272-BAG-T-TR STMicroelectronics, F272-BAG-T-TR Datasheet - Page 165

• Manufacturer Part Number: F272-BAG-T-TR
• Description: MCU 16BIT 256K FLASH 144-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of F272-BAG-T-TR

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-TQFP, 144-VQFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: ASC, CAN, I2C, SSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

ST10F272B/ST10F272E
Table 78.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
38
39
41
82
83
46
47
48
49
50
51
53
68
55
57
Symbol
CC
SR
CC
CC
CC
SR
SR
CC
CC
CC
SR
SR
SR
CC
CC
ALE falling edge to Latched
CS
Latched CS low to Valid Data
In
Latched CS hold after RD,
WR
Address setup to RdCS,
WrCS
(with RW-delay)
Address setup to RdCS,
WrCS
(no RW-delay)
RdCS to Valid Data In
(with RW-delay)
RdCS to Valid Data In
(no RW-delay)
RdCS, WrCS Low Time
(with RW-delay)
RdCS, WrCS Low Time
(no RW-delay)
Data valid to WrCS
Data hold after RdCS
Data float after RdCS
(with RW-delay)
Data float after RdCS
(no RW-delay)
Address hold after
RdCS, WrCS
Data hold after WrCS
Demultiplexed bus timings (continued)
1. RW-delay and t
2. Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
3. Partially tested, guaranteed by design characterization.
Therefore address changes before the end of RD have no impact on read cycles.
Parameter
3
3
A
refer to the next following bus cycle.
– 8.5 + t
15.5 + t
14 + 2t
– 4 – t
2 + 2t
28 + t
10 + t
2 + t
2 + t
min.
F
–
–
–
0
–
–
TCL = 12.5 ns
CPU
F
F
A
C
C
A
A
C
F
= 40 MHz
+ t
16.5 + t
16.5 + t
16.5 +
4 + t
6 – t
4 + t
max.
C
–
–
–
–
–
–
–
–
–
+ 2t
A
C
F
C
F
A
2TCL – 11 + 2t
TCL –10.5 + 2t
2TCL – 9.5 + t
3TCL – 9.5 + t
TCL – 10.5 + t
TCL – 10.5 + t
2TCL – 15 + t
– 8.5 + t
– 4 – t
min.
1/2 TCL = 1 to 64MHz
Variable CPU Clock
–
–
–
0
–
–
A
F
Electrical characteristics
C
C
C
F
F
A
A
2TCL – 8.5 + t
2TCL – 21 + t
3TCL – 21 + t
TCL – 8.5 + t
3TCL – 21 +
+ t
6 – t
max.
C
–
–
–
–
–
–
–
–
–
+ 2t
A
A
F
C
C
F
165/182
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns