ST10F272M-4T3 STMicroelectronics, ST10F272M-4T3 Datasheet - Page 144
ST10F272M-4T3
Manufacturer Part Number
ST10F272M-4T3
Description
MCU 16BIT 256K FLASH 144-LQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet
1.ST10F272M-4TR3.pdf
(176 pages)
Specifications of ST10F272M-4T3
Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-MQFP, 144-PQFP
Processor Series
ST10F27x
Core
ST10
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST10F272M-4T3
Manufacturer:
STMicroelectronics
Quantity:
10 000
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Electrical characteristics
24.8.7
144/176
an external clock failure occurs, then the watchdog counter overflows (after 16 PLL clock
cycles).
The CPU clock signal will be switched to the PLL free-running clock signal, and the oscillator
watchdog interrupt request is flagged. The CPU clock will not switch back to the external
clock even if a valid external clock exits on XTAL1 pin. Only a hardware reset (or
bidirectional software/watchdog reset) can switch the CPU clock source back to direct clock
input.
When the OWD is disabled, the CPU clock is always the external oscillator clock (in direct
drive or prescaler operation) and the PLL is switched off to decrease consumption supply
current.
Phase locked loop (PLL)
For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked
loop is enabled and it provides the CPU clock (see
frequency by the factor F which is selected via the combination of pins P0.15-13 (f
f
the input clock. This synchronization is done smoothly, so the CPU clock frequency does not
change abruptly.
Due to this adaptation to the input clock the frequency of f
locked to f
individual TCLs.
The timings listed in the AC characteristics that refer to TCLs therefore must be calculated
using the minimum TCL that is possible under the respective circumstances.
The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes f
keep it locked on f
one TCL period.
This is especially important for bus cycles using wait states and for example, such as for the
operation of timers or serial interfaces. For all slower operations and longer periods (for
example, pulse train generation or measurement, or lower baudrates) the deviation caused
by the PLL jitter is negligible. Refer to next
XTAL
x F). With every F’th transition of f
XTAL
. The slight variation causes a jitter of f
XTAL
. The relative deviation of TCL is the maximum when it is referred to
XTAL
Section 24.8.9: PLL jitter
the PLL circuit synchronizes the CPU clock to
Table
CPU
61). The PLL multiplies the input
which also effects the duration of
CPU
is constantly adjusted so it is
for more details.
ST10F272M
CPU
CPU
to
=
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