ST10F272M-4T3 STMicroelectronics, ST10F272M-4T3 Datasheet - Page 77

• Manufacturer Part Number: ST10F272M-4T3
• Description: MCU 16BIT 256K FLASH 144-LQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F272M-4T3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Processor Series: ST10F27x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F272M
20
20.1
System reset
System reset initializes the MCU in a predefined state. There are six ways to activate a reset
state. The system start-up configuration is different for each case as shown in
Table 41.
1. RSTIN pulse should be longer than 500 ns (filter) and than settling time for configuration of Port0.
2. See next
3. The RPD status has no influence unless bidirectional reset is activated (bit BDRSTEN in SYSCON): RPD
The figures in the upcoming sections 20.2, 20.3,
terminology:
●
●
Input filter
On the RSTIN input pin an on-chip RC filter is implemented. It is sized to filter all spikes
shorter than 50ns. On the other hand, a valid pulse longer than 500 ns is required for the
ST10 to recognize a reset command. In between 50 ns and 500 ns a pulse can either be
filtered or recognized as valid, depending on the operating conditions and process
variations.
For this reason all minimum durations mentioned in this chapter for the different kinds of
reset events must be carefully evaluated, taking into account the above requirements.
In particular, for short hardware reset, where only 4 TCL is specified as minimum input reset
pulse duration, the operating frequency is a key factor.
Examples:
●
●
Power-on reset
Asynchronous hardware reset
Synchronous long hardware
reset
Synchronous short hardware
reset
Watchdog timer reset
Software reset
low inhibits the bidirectional reset on SW and WDT reset events, that is RSTIN is not activated (refer to
Sections 20.4,
Transparent: Level of the pin affects the internal reset logic
Not transparent: Level of the pin does not affect internal logic
For a CPU clock of 40 MHz, 4 TCL is 50 ns, so it would be filtered. In this case the
minimum becomes the one imposed by the filter (that is 500 ns).
For a CPU clock of 4 MHz, 4 TCL is 500 ns. In this case the minimum from the formula
is coherent with the limit imposed by the filter.
Reset source
Section 20.1
Reset event definition
20.5
and 20.6).
for more details on minimum reset pulse duration.
SHWR
WDTR
LHWR
PONR
SWR
Flag
status
RPD
High
High
Low
Low
(3)
(3)
Power-on
t
t
t
t
WDT overflow
SRST instruction execution
RSTIN
RSTIN
RSTIN
RSTIN
20.5
>
> max(4 TCL, 500ns)
> (1032 + 12) TCL + max(4 TCL, 500ns)
< (1032 + 12) TCL + max(4 TCL, 500ns)
(1)
and
20.6
Conditions
use the following
(2)
System reset
Table
41.
77/176
(2)
(2)