ST10F272M-4T3 STMicroelectronics, ST10F272M-4T3 Datasheet - Page 75

• Manufacturer Part Number: ST10F272M-4T3
• Description: MCU 16BIT 256K FLASH 144-LQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F272M-4T3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Processor Series: ST10F27x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F272M
18
Real-time clock
The real-time clock is an independent timer, in which the clock is derived directly from the
clock oscillator on XTAL1 (main oscillator) input or XTAL3 input (32 kHz low-power oscillator)
so that it can continue running even in Idle or power-down modes (if so enabled). Registers
access is implemented onto the XBUS. This module is designed with the following
characteristics:
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The real-time clock is based on two main blocks of counters. The first block is a prescaler
which generates a basic reference clock (for example, a 1 second period). This basic
reference clock is provided by the 20-bit divider. This 20-bit counter is driven by an input
clock derived from the on-chip CPU clock, predivided by a 1/64 fixed counter. This 20-bit
counter is loaded at each basic reference clock period with the value of the 20-bit prescaler
register. The value of the 20-bit RTCP register determines the period of the basic reference
clock.
A timed interrupt request (RTCSI) may be sent on each basic reference clock period. The
second block of the RTC is a 32-bit counter that may be initialized with the current system
time. This counter is driven with the basic reference clock signal. In order to provide an
alarm function the contents of the counter is compared with a 32-bit alarm register. The
alarm register may be loaded with a reference date. An alarm interrupt request (RTCAI),
may be generated when the value of the counter matches the alarm register.
The timed RTCSI and the alarm RTCAI interrupt requests can trigger a fast external
interrupt via the EXISEL register of port 2 and wake up the ST10 chip when running power-
down mode. Using the RTCOFF bit of the RTCCON register, the user may switch off the
clock oscillator when entering the power-down mode.
The last function implemented in the RTC is to switch off the main on-chip oscillator and the
32 kHz on chip oscillator if the ST10 enters the power-down mode, so that the chip can be
fully switched off (if RTC is disabled).
At power-on, and after reset phase, if the presence of a 32 kHz oscillation on XTAL3/XTAL4
pins is detected, then the RTC counter is driven by this low frequency reference clock: when
Power-down mode is entered, the RTC can either be stopped or left running, and in both the
cases the main oscillator is turned off, reducing the power consumption of the device to the
minimum required to keep on running the RTC counter and relative reference oscillator. This
is also valid if stand-by mode is entered (switching off the main supply V
RTC and the low power oscillator (32 kHz) are biased by the V
power on and after Reset, the 32 kHz is not present, the main oscillator drives the RTC
counter, and since it is powered by the main power supply, it cannot be maintained running
in stand-by mode, while in power-down mode the main oscillator is maintained running to
provide the reference to the RTC module (if not disabled).
Generation of the current time and date for the system
Cyclic time based interrupt, on port2 external interrupts every ‘RTC basic clock tick’
and after n ’RTC basic clock ticks’ (n is programmable) if enabled
58-bit timer for long term measurement
Capability to exit the ST10 chip from power-down mode (if PWDCFG of SYSCON set)
after a programmed delay
STBY
. Vice versa, when at
DD
), since both the
Real-time clock
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