ST10F272M-4T3 STMicroelectronics, ST10F272M-4T3 Datasheet - Page 168

• Manufacturer Part Number: ST10F272M-4T3
• Description: MCU 16BIT 256K FLASH 144-LQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F272M-4T3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Processor Series: ST10F27x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Electrical characteristics
Table 74.
1. When 40 MHz CPU clock is used the maximum baudrate cannot be higher than 6.6Mbaud (<SSCBR> = ‘2h’) due to the
2. Formula for SSC clock cycle time: t
3. Partially tested, guaranteed by design characterization.
Figure 61. SSC master timing
1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift
2. The bit timing is repeated for all bits to be transmitted or received.
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t
t
t
t
Symbol
307p
308p
307
308
limited granularity of <SSCBR>. Value ‘1h’ for <SSCBR> can be used only with CPU clock equal to (or lower than) 32 MHz.
baudrate register, taken as unsigned 16-bit integer. Minimum limit allowed for t
edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high
transition (SSCPO = 0b).
SR
SR
SR
SR
MTSR
MRST
SCLK
Read data setup time before latch
edge, phase error detection on
(SSCPEN = 1)
Read data hold time after latch
edge, phase error detection on
(SSCPEN = 1)
Read data setup time before latch
edge, phase error detection off
(SSCPEN = 0)
Read data hold time after latch
edge, phase error detection off
(SSCPEN = 0)
SSC master mode timings (continued)
(1)
Parameter
t
305
t
307
1st in bit
t
1st out bit
300
300
t
308
= 4 TCL x (<SSCBR> + 1) Where <SSCBR> represents the content of the SSC
t
305
t
301
t
304
2nd out bit
t
2nd in bit
302
(<SSCBR> = 0002h)
Maximum baudrate
37.5
Min
50
25
@ f
0
6.6 Mbaud
t
CPU
303
t
306
= 40 MHz
(1)
Max
(2)
–
–
–
–
300
t
is 125 ns (corresponding to 8 Mbaud).
305
t
(<SSCBR> = 0001h - FFFFh)
307
Last in bit
2TCL + 12.5
Last out bit
4TCL
2TCL
Min
t
Variable baudrate
308
0
Max
–
–
–
–
ST10F272M
Unit
ns
ns
ns
ns