ST10F272M-4T3 STMicroelectronics, ST10F272M-4T3 Datasheet - Page 23

• Manufacturer Part Number: ST10F272M-4T3
• Description: MCU 16BIT 256K FLASH 144-LQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F272M-4T3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Processor Series: ST10F27x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F272M
Note:
X-miscellaneous: Address range 00’EB00h - 00’EBFFh is reserved for the access to a set
of XBUS additional features. They are enabled by setting XPEN bit 2 of the SYSCON
register and bit 10 of the XPERCON register. Accesses to this additional features use
demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two
waitstates give an access time of 100ns at 40 MHz CPU clock. No tristate waitstate is used.
The following set of features are provided:
●
●
●
●
●
●
●
●
●
In order to meet the needs of designs where more memory is required than is provided on
chip, up to 16 Mbytes of external memory can be connected to the microcontroller.
Visibility of XBUS peripherals
In order to keep the ST10F272M compatible with the ST10F168/ST10F269, the XBUS
peripherals can be selected to be visible on the external address / data bus. Different bits for
X-peripheral enabling in XPERCON register must be set. If these bits are cleared before the
global enabling with XPEN bit in SYSCON register, the corresponding address space, port
pins and interrupts are not occupied by the peripherals, thus the peripheral is not visible and
not available. Refer to
XPERCON and X-peripheral clock gating
As already mentioned, the XPERCON register must be programmed to enable the single X-
bus modules separately. The XPERCON is a read/write ESFR register.
The new feature of clock gating has been implemented by means of this register: Once the
EINIT instruction has been executed, all the peripherals (except RAMs and XMISC) not
enabled in the XPERCON register are not be clocked. The clock gating can reduce power
consumption and improve EMI when the user doesn’t use all X-peripherals.
When the clock has been gated in the disabled peripherals, no reset will be raised once the
EINIT instruction has been executed.
CLKOUT programmable divider
XBUS interrupt management registers
ADC multiplexing on P1L register
Port1L digital disable register for extra ADC channels
CAN2 multiplexing on P4.5/P4.6
CAN1-2 main clock prescaler
Main voltage regulator disable for power-down mode
TTL/CMOS threshold selection for port0, port1, and port5
Flash temporary unprotection
Chapter 23: Register set on page
108.
Memory organization
23/176