C8051F521A-IM Silicon Laboratories Inc, C8051F521A-IM Datasheet - Page 106

• Manufacturer Part Number: C8051F521A-IM
• Description: IC 8051 MCU 8K FLASH 10DFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F52xr

Specifications of C8051F521A-IM

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 10-DFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 6
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F500DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1488 - KIT DEV C8051F53XA, C8051F52XA770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1455 - ADAPTER PROGRAM TOOLSTICK F520
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1490-5

C8051F52x/F52xA/F53x/F53xA
11. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:




All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled dur-
ing and after the reset. For V
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator. Refer to Section “14. Oscillators” on page 134 for information on selecting and configuring
the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its clock
source (Section “19.3. Watchdog Timer Mode” on page 202 details the use of the Watchdog Timer). Pro-
gram execution begins at location 0x0000.
106
Px.x
Px.x
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled.
System
Clock
Comparator 0
+
-
C0RSEF
Detector
Missing
Clock
(one-
shot)
Microcontroller
EN
Extended Interrupt
DD
CIP-51
Core
Handler
Monitor and power-on resets, the RST pin is driven low until the device
WDT
PCA
Figure 11.1. Reset Sources
EN
VDD
System Reset
Supply
Monitor
+
-
Rev. 1.3
Enable
(Software Reset)
SWRSF
'0'
Power On
Reset
Illegal Flash
Operation
(wired-OR)
Funnel
Reset
/RST