C8051F521A-IM Silicon Laboratories Inc, C8051F521A-IM Datasheet - Page 46
C8051F521A-IM
Manufacturer Part Number
C8051F521A-IM
Description
IC 8051 MCU 8K FLASH 10DFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F52xr
Specifications of C8051F521A-IM
Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
10-DFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
6
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 6x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
6
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F500DK
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1488 - KIT DEV C8051F53XA, C8051F52XA770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1455 - ADAPTER PROGRAM TOOLSTICK F520
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1490-5
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C8051F52x/F52xA/F53x/F53xA
Table 3.7. Pin Definitions for the C8051F53x and C805153xA (QFN 20)
46
Note: Please refer to Section “20. Device Specific Behavior” on page 209.
CNVSTR
V
Name
C2CK
RST/
P0.0/
V
P1.2/
GND
P1.7
P1.6
P1.5
P1.4
P1.3
P1.1
REGIN
V
REF
DD
‘F53xA ‘F53x
Pin Numbers
10
11
12
1
2
3
4
5
6
7
8
9
10
12
11
1
2
3
4
5
6
7
8
9
D I/O or
D I/O or
D I/O or
D I/O or
D I/O or
D I/O or
D I/O or
D I/O or
A O or
D I/O
D I/O
Type
D In
D In
A In
A In
A In
A In
A In
A In
A In
A In
Description
Device Reset. Open-drain output of internal POR or V
An external source can initiate a system reset by driving this pin
low for at least the minimum RST low time to generate a system
reset, as defined in Table 2.7 on page 32. A 1 k pullup to V
is recommended. See Reset Sources Section for a complete
description.
Clock signal for the C2 Debug Interface.
Port 0.0. See Port I/O Section for a complete description.
External V
Ground.
Core Supply Voltage.
On-Chip Voltage Regulator Input.
Port 1.7. See Port I/O Section for a complete description.
Port 1.6. See Port I/O Section for a complete description.
Port 1.5. See Port I/O Section for a complete description.
Port 1.4. See Port I/O Section for a complete description.
Port 1.3. See Port I/O Section for a complete description.
Port 1.2. See Port I/O Section for a complete description.
External Converter start input for the ADC0, see Section “4. 12-Bit
ADC (ADC0)” on page 52 for a complete description.
Port 1.1. See Port I/O Section for a complete description.
Rev. 1.3
REF
Input. See V
REF
Section.
DD
monitor.
REGIN
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