C8051F521A-IM Silicon Laboratories Inc, C8051F521A-IM Datasheet - Page 164

• Manufacturer Part Number: C8051F521A-IM
• Description: IC 8051 MCU 8K FLASH 10DFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F52xr

Specifications of C8051F521A-IM

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 10-DFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 6
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F500DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1488 - KIT DEV C8051F53XA, C8051F52XA770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1455 - ADAPTER PROGRAM TOOLSTICK F520
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1490-5

C8051F52x/F52xA/F53x/F53xA
17.1. Software Interface with the LIN Peripheral
The selection of the mode (Master or Slave) and the automatic baud rate feature are done though the LIN0
Control Mode (LIN0CF) register. The other LIN registers are accessed indirectly through the two SFRs
LIN0 Address (LINADDR) and LIN0 Data (LINDATA). The LINADDR register selects which LIN register is
targeted by reads/writes of the LINDATA register. The full list of indirectly-accessible LIN register is given in
Table 17.4 on page 173.
17.2. LIN Interface Setup and Operation
The hardware based LIN peripheral allows for the implementation of both Master and Slave nodes with
minimal firmware overhead and complete control of the interface status while allowing for interrupt and
polled mode operation.
The first step to use the peripheral is to define the basic characteristics of the node:



17.2.1. Mode Definition
Following the LIN specification, the peripheral implements both the Slave and Master operating modes in
hardware. The mode is configured using the MODE bit (LIN0CF.6).
17.2.2. Baud Rate Options: Manual or Autobaud
The LIN peripheral can be selected to have its baud rate calculated manually or automatically. A master
node must always have its baud rate set manually, but slave nodes can choose between a manual or auto-
matic setup. The configuration is selected using the ABAUD bit (LIN0CF.5).
Both the manual and automatic baud rate configurations require additional setup. The following sections
explain the different options available and their relation with the baud rate, along with the steps necessary
to achieve the required baud rate.
17.2.3. Baud Rate Calculations—Manual Mode
The baud rate used by the peripheral is a function of the System Clock (SYSCLK) and the bit-timing Reg-
isters according to the following equation:
The prescaler, divider and multiplier factors are part of the LIN0DIV and LIN0MUL registers and can
assume values in the following range:
164
Mode—Master or Slave
Baud Rate—Either defined manually or using the autobaud feature (slave mode only).
Checksum Type—Select between classic or enhanced checksum, both of which are implemented in
hardware.
baud_rate
=
------------------------------------------------------------------------------------------------------ -
2

prescaler
+
Rev. 1.3
1


divider
SYSCLK


multiplier
+
1
