C8051F521A-IM Silicon Laboratories Inc, C8051F521A-IM Datasheet - Page 185
C8051F521A-IM
Manufacturer Part Number
C8051F521A-IM
Description
IC 8051 MCU 8K FLASH 10DFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F52xr
Specifications of C8051F521A-IM
Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
10-DFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
6
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 6x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
6
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F500DK
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1488 - KIT DEV C8051F53XA, C8051F52XA770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1455 - ADAPTER PROGRAM TOOLSTICK F520
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1490-5
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SFR Definition 18.1. TCON: Timer Control
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
TF1
R/W
Bit7
TF1: Timer 1 Overflow Flag.
Set by hardware when Timer 1 overflows. This flag can be cleared by software but is auto-
matically cleared when the CPU vectors to the Timer 1 interrupt service routine.
0: No Timer 1 overflow detected.
1: Timer 1 has overflowed.
TR1: Timer 1 Run Control.
0: Timer 1 disabled.
1: Timer 1 enabled.
TF0: Timer 0 Overflow Flag.
Set by hardware when Timer 0 overflows. This flag can be cleared by software but is auto-
matically cleared when the CPU vectors to the Timer 0 interrupt service routine.
0: No Timer 0 overflow detected.
1: Timer 0 has overflowed.
TR0: Timer 0 Run Control.
0: Timer 0 disabled.
1: Timer 0 enabled.
IE1: External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It can be
cleared by software but is automatically cleared when the CPU vectors to the External Inter-
rupt 1 service routine if IT1 = 1. When IT1 = 0, this flag is set to 1 when INT0 is active as
defined by bit IN1PL in register IT01CF (see SFR Definition 10.5. “IT01CF: INT0/INT1 Con-
figuration” on page 105).
IT1: Interrupt 1 Type Select.
This bit selects whether the configured INT0 interrupt will be edge or level sensitive. INT0 is
configured active low or high by the IN1PL bit in the IT01CF register (see SFR
Definition 10.5. “IT01CF: INT0/INT1 Configuration” on page 105).
0: INT0 is level triggered.
1: INT0 is edge triggered.
IE0: External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT0 is detected. It can be
cleared by software but is automatically cleared when the CPU vectors to the External Inter-
rupt 0 service routine if IT0 = 1. When IT0 = 0, this flag is set to 1 when INT0 is active as
defined by bit IN0PL in register IT01CF (see SFR Definition 10.5. “IT01CF: INT0/INT1 Con-
figuration” on page 105).
IT0: Interrupt 0 Type Select.
This bit selects whether the configured INT0 interrupt will be edge or level sensitive. INT0 is
configured active low or high by the IN0PL bit in register IT01CF (see SFR Definition 10.5.
“IT01CF: INT0/INT1 Configuration” on page 105).
0: INT0 is level triggered.
1: INT0 is edge triggered.
TR1
R/W
Bit6
TF0
R/W
Bit5
TR0
R/W
Bit4
C8051F52x/F52xA/F53x/F53xA
Rev. 1.3
R/W
IE1
Bit3
R/W
IT1
Bit2
R/W
IE0
Bit1
SFR Address:
R/W
IT0
Bit0
Addressable
Reset Value
00000000
0x88
Bit
185
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