C8051F521A-IM Silicon Laboratories Inc, C8051F521A-IM Datasheet - Page 205

IC 8051 MCU 8K FLASH 10DFN

C8051F521A-IM

Manufacturer Part Number
C8051F521A-IM
Description
IC 8051 MCU 8K FLASH 10DFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F52xr
Datasheets

Specifications of C8051F521A-IM

Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
10-DFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
6
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 6x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
6
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F500DK
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1488 - KIT DEV C8051F53XA, C8051F52XA770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1455 - ADAPTER PROGRAM TOOLSTICK F520
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1490-5
19.4. Register Descriptions for PCA
Following are detailed descriptions of the special function registers related to the operation of the PCA.
SFR Definition 19.1. PCA0CN: PCA Control
Bit7:
Bit6:
Bits5–3: Reserved.
Bit2:
Bit1:
Bit0:
R/W
CF
Bit7
CF: PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000. When the
Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to vector
to the PCA interrupt service routine. This bit is not automatically cleared by hardware and
must be cleared by software.
CR: PCA Counter/Timer Run Control.
This bit enables/disables the PCA Counter/Timer.
0: PCA Counter/Timer disabled.
1: PCA Counter/Timer enabled.
CCF2: PCA Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF2 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF1: PCA Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF1 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF0: PCA Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF0 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
R/W
CR
Bit6
Reserved Reserved Reserved
R/W
Bit5
R/W
Bit4
C8051F52x/F52xA/F53x/F53xA
Rev. 1.3
R/W
Bit3
CCF2
R/W
Bit2
CCF1
R/W
Bit1
SFR Address: 0xD8
CCF0
R/W
Bit0
00000000
Addressable
Reset Value
Bit
205

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