MC56F8346VFVER2 Freescale Semiconductor, MC56F8346VFVER2 Datasheet - Page 113

• Manufacturer Part Number: MC56F8346VFVER2
• Description: IC HYBRID CTRLR 16BIT 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8346VFVER2

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 62
• Program Memory Size: 136KB (68K x 16)
• Program Memory Type: FLASH
• Ram Size: 6K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• For Use With: MC56F8367EVME - EVAL BOARD FOR MC56F83X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.5.1
6.5.1.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.1.2
This bit reflects the current (non-clocked) state of the EMI_MODE pin. During reset, this bit, coupled with
the EXTBOOT signal, is used to initialize address bits [19:16] either as GPIO or as address. These settings
can be explicitly overwritten using the appropriate GPIO peripheral enable register at any time after reset.
In addition, this pin can be used as a general purpose input pin after reset.
6.5.1.3
6.5.1.4
This bit is always read as 0. Writing a 1 to this field will cause the part to reset.
6.5.1.5
Freescale Semiconductor
Preliminary
•
•
•
•
•
•
$C
$D
$E
Base + $0
RESET
0 = External address bits [19:16] are initially programmed as GPIO
1 = When booted with EXTBOOT = 1, A[19:16] are initially programmed as address. If EXTBOOT is 0,
they are initialized as GPIO.
0 = OnCE clock to 56800E core enabled when core TAP is enabled
1 = OnCE clock to 56800E core is always enabled
00 - STOP mode will be entered when the 56800E core executes a STOP instruction
01 - The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can be
reprogrammed in the future
Read
Write
SIM_ISALH
SIM_ISALL
SIM_PCE
SIM Control Register (SIM_CONTROL)
Reserved—Bits 15–7
EMI_MODE (EMI_MODE)—Bit 6
OnCE Enable (OnCE EBL)—Bit 5
Software Reset (SWRST)—Bit 4
Stop Disable (STOP_DISABLE)—Bits 3–2
15
W
W
W
0
0
R
R
R
EMI
Figure 6-2 SIM Register Map Summary (Continued)
1
14
Figure 6-3 SIM Control Register (SIM_CONTROL)
0
0
= Reserved
ADCB
1
13
0
0
ADCA
1
12
0
0
CAN
1
56F8346 Technical Data, Rev. 15
11
0
0
DEC1
1
10
0
0
DEC0 TMRD TMRC TMRB TMRA
1
9
0
0
1
8
0
0
ISAL[21:6]
1
7
0
0
1
MODE
EMI_
6
0
1
ONCE
EBL
5
0
SCI1
1
RST
SW
4
0
SCI0
1
3
0
DISABLE
SPI1
STOP_
1
2
0
SPI0
Register Descriptions
1
PWM
1
DISABLE
0
ISAL[23:22]
B
WAIT_
PWM
0
0
A
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