MC56F8346VFVER2 Freescale Semiconductor, MC56F8346VFVER2 Datasheet - Page 28

• Manufacturer Part Number: MC56F8346VFVER2
• Description: IC HYBRID CTRLR 16BIT 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8346VFVER2

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 62
• Program Memory Size: 136KB (68K x 16)
• Program Memory Type: FLASH
• Ram Size: 6K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• For Use With: MC56F8367EVME - EVAL BOARD FOR MC56F83X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

28
Signal Name
(GPIOE1)
(GPIOD6)
(GPIOD7)
RXD0
RXD1
TXD1
TMS
TCK
TDI
Table 2-2 Signal and Package Information for the 144 Pin LQFP
Pin No.
121
122
123
42
43
5
Schmitt
Schmitt
Schmitt
Output
Output
Output
Output
Input/
Input/
Input/
Type
Input
Input
Input
Input
Input
pulled high
pulled high
pulled low
disabled,
pull-up is
internally
internally
internally
output is
enabled
In reset,
enabled
enabled
During
pull-up
pull-up
56F8346 Technical Data, Rev. 15
Reset
Input,
Input,
Input,
Input,
Input,
State
Receive Data — SCI0 receive data input
Port E GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 1 in the
GPIOE_PUR register.
Transmit Data — SCI1 transmit data output
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 6 in the
GPIOD_PUR register.
Receive Data — SCI1 receive data input
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is SCI input.
To deactivate the internal pull-up resistor, clear bit 7 in the
GPIOD_PUR register.
Test Clock Input — This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/EOnCE
port. The pin is connected internally to a pull-down resistor.
Test Mode Select Input — This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.
To deactivate the internal pull-up resistor, set the JTAG bit in the
SIM_PUDR register.
Note:
Test Data Input — This input pin provides a serial input data
stream to the JTAG/EOnCE port. It is sampled on the rising edge
of TCK and has an on-chip pull-up resistor.
To deactivate the internal pull-up resistor, set the JTAG bit in the
SIM_PUDR register.
Always tie the TMS pin to V
Signal Description
DD
through a 2.2K resistor.
Freescale Semiconductor
Preliminary