MC56F8346VFVER2 Freescale Semiconductor, MC56F8346VFVER2 Datasheet - Page 33

• Manufacturer Part Number: MC56F8346VFVER2
• Description: IC HYBRID CTRLR 16BIT 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8346VFVER2

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 62
• Program Memory Size: 136KB (68K x 16)
• Program Memory Type: FLASH
• Ram Size: 6K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• For Use With: MC56F8367EVME - EVAL BOARD FOR MC56F83X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Freescale Semiconductor
Preliminary
Signal Name
PHASEB1
(GPIOC1)
(MOSI1)
(TB1)
Table 2-2 Signal and Package Information for the 144 Pin LQFP
Pin No.
7
Schmitt
Schmitt
Schmitt
Schmitt
Output
Output
Output
Input/
Input/
Input/
Type
Input
enabled
During
pull-up
56F8346 Technical Data, Rev. 15
Reset
Input,
State
Phase B1 — Quadrature Decoder 1, PHASEB input for decoder 1.
TB1 — Timer B, Channel 1
SPI 1 Master Out/Slave In — This serial data pin is an output from
a master device and an input to a slave device. The master device
places data on the MOSI line a half-cycle before the clock edge the
slave device uses to latch the data. To activate the SPI function,
set the PHSB_ALT bit in the SIM_GPS register. For details, see
Part
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
In the 56F8346, the default state after reset is PHASEB1.
In the 56F8146, the default state is not one of the functions offered
and must be reconfigured.
To deactivate the internal pull-up resistor, clear bit 1 in the
GPIOC_PUR register.
6.5.8.
Signal Description
Signal Pins
33