MC56F8346VFVER2 Freescale Semiconductor, MC56F8346VFVER2 Datasheet - Page 38

• Manufacturer Part Number: MC56F8346VFVER2
• Description: IC HYBRID CTRLR 16BIT 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8346VFVER2

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 62
• Program Memory Size: 136KB (68K x 16)
• Program Memory Type: FLASH
• Ram Size: 6K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• For Use With: MC56F8367EVME - EVAL BOARD FOR MC56F83X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

38
Signal Name
(GPIOE10)
(GPIOE11)
RESET
RSTO
IRQA
IRQB
TD0
TD1
Table 2-2 Signal and Package Information for the 144 Pin LQFP
Pin No.
116
117
54
55
86
85
Schmitt
Schmitt
Schmitt
Schmitt
Output
Output
Output
Input/
Input/
Type
Input
Input
enabled
enabled
enabled
During
pull-up
pull-up
pull-up
Output
56F8346 Technical Data, Rev. 15
Reset
Input,
Input,
Input,
State
TD0 -1 — Timer D, Channels 0 and 1
Port E GPIO — These GPIO pins can be individually programmed
as input or output pins.
At reset, these pins default to Timer functionality.
To deactivate the internal pull-up resistor, clear the appropriate bit
of the GPIOE_PUR register. See
External Interrupt Request A and B — The IRQA and IRQB
inputs are asynchronous external interrupt requests during Stop
and Wait mode operation. During other operating modes, they are
synchronized external interrupt requests, which indicate an
external device is requesting service. They can be programmed to
be level-sensitive or negative-edge triggered.
To deactivate the internal pull-up resistor, set the IRQ bit in the
SIM_PUDR register. See
Reset — This input is a direct hardware reset on the processor.
When RESET is asserted low, the device is initialized and placed
in the reset state. A Schmitt trigger input is used for noise
immunity. When the RESET pin is deasserted, the initial chip
operating mode is latched from the EXTBOOT pin. The internal
reset signal will be deasserted synchronous with the internal clocks
after a fixed number of internal clocks.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and the
JTAG/EOnCE module must not be reset. In this case, assert
RESET but do not assert TRST.
Note: The internal Power-On Reset will assert on initial power-up.
To deactivate the internal pull-up resistor, set the RESET bit in the
SIM_PUDR register. See
Reset Output — This output reflects the internal reset state of the
chip.
Signal Description
Part 6.5.6
Part 6.5.6
Part 6.5.6
for details.
for details.
Freescale Semiconductor
for details.
Preliminary