MC56F8346VFVER2 Freescale Semiconductor, MC56F8346VFVER2 Datasheet - Page 164

• Manufacturer Part Number: MC56F8346VFVER2
• Description: IC HYBRID CTRLR 16BIT 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8346VFVER2

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 62
• Program Memory Size: 136KB (68K x 16)
• Program Memory Type: FLASH
• Ram Size: 6K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LQFP
• For Use With: MC56F8367EVME - EVAL BOARD FOR MC56F83X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

at the same time that S3 is closed/open. When S1/S2 are closed & S3 is open, one input of the sample and
hold circuit moves to V
switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended
analog input is switched to a differential voltage centered about V
on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). Note that there
are additional capacitances associated with the analog input pad, routing, etc., but these do not filter into
the S/H output voltage, as S1 provides isolation during the charge-sharing phase.
One aspect of this circuit is that there is an on-going input current, which is a function of the analog input
voltage, V
164
1.
2.
3.
4.
Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pf
Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pf
Equivalent resistance for the ESD isolation resistor and the channel select mux; 500 ohms
Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only
connected to it at sampling time; 1pf
REF
Analog Input
and the ADC clock frequency.
1
REFH
Figure 10-23 Equivalent Circuit for A/D Loading
- V
REFH
2
56F8346 Technical Data, Rev. 15
/ 2, while the other charges to the analog input voltage. When the
(V
REFH
3
- V
REFLO
) / 2
S1
S2
4
S3
REFH
C1
C2
S/H
- V
REFH
C1 = C2 = 1pF
/ 2. The switches switch
Freescale Semiconductor
Preliminary