DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 11

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.6
5.7
5.8
Section 6 Interrupt Controller (INTC) ...................................................................91
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
Section 7 User Break Controller (UBC) ..............................................................115
7.1
7.2
5.5.4
Cases when Exceptions are Accepted .................................................................................. 85
Stack States after Exception Handling Ends........................................................................ 86
Usage Notes ......................................................................................................................... 88
5.8.1
5.8.2
5.8.3
5.8.4
Features................................................................................................................................ 91
Input/Output Pins................................................................................................................. 93
Register Descriptions ........................................................................................................... 94
6.3.1
6.3.2
6.3.3
6.3.4
Interrupt Sources................................................................................................................ 104
6.4.1
6.4.2
6.4.3
Interrupt Exception Handling Vector Table....................................................................... 106
Interrupt Operation ............................................................................................................ 109
6.6.1
6.6.2
Interrupt Response Time.................................................................................................... 112
Usage Note......................................................................................................................... 114
6.8.1
6.8.2
Features.............................................................................................................................. 115
Register Descriptions ......................................................................................................... 117
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
General Illegal Instructions..................................................................................... 84
Value of Stack Pointer (SP) .................................................................................... 88
Value of Vector Base Register (VBR) .................................................................... 88
Address Errors Caused by Stacking for Address Error Exception Handling.......... 88
Notes on Slot Illegal Instruction Exception Handling ............................................ 89
Interrupt Control Register 0 (ICR0)........................................................................ 95
IRQ Control Register (IRQCR) .............................................................................. 96
IRQ Status register (IRQSR) .................................................................................. 98
Interrupt Priority Registers A to F and H to M
(IPRA to IPRF and IPRH to IPRM) ..................................................................... 101
External Interrupts ................................................................................................ 104
On-Chip Peripheral Module Interrupts ................................................................. 105
User Break Interrupt ............................................................................................. 105
Interrupt Sequence ................................................................................................ 109
Stack after Interrupt Exception Handling ............................................................. 112
Clearing Interrupt Source Flags ............................................................................ 114
NMI Not Used ...................................................................................................... 114
Break Address Register A (BARA) ...................................................................... 118
Break Address Mask Register A (BAMRA)......................................................... 118
Break Bus Cycle Register A (BBRA)................................................................... 119
Break Data Register A (BDRA) ........................................................................... 121
Break Data Mask Register A (BDMRA) .............................................................. 122
Break Address Register B (BARB) ...................................................................... 123
Rev. 5.00 Mar. 06, 2009 Page ix of xviii
REJ09B0243-0500