DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 14

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.7
9.8
Section 10 Port Output Enable (POE) .................................................................383
10.1 Features.............................................................................................................................. 383
10.2 Input/Output Pins............................................................................................................... 385
10.3 Register Descriptions ......................................................................................................... 386
Rev. 5.00 Mar. 06, 2009 Page xii of xviii
REJ09B0243-0500
9.6.2
Usage Notes ....................................................................................................................... 334
9.7.1
9.7.2
9.7.3
9.7.4
9.7.5
9.7.6
9.7.7
9.7.8
9.7.9
9.7.10 Contention between TGR Write and Input Capture.............................................. 341
9.7.11 Contention between Buffer Register Write and Input Capture ............................. 342
9.7.12 TCNT_2 Write and Overflow/Underflow Contention in Cascade Connection .... 342
9.7.13 Counter Value during Complementary PWM Mode Stop .................................... 344
9.7.14 Buffer Operation Setting in Complementary PWM Mode ................................... 344
9.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag .................. 345
9.7.16 Overflow Flags in Reset Synchronous PWM Mode ............................................. 346
9.7.17 Contention between Overflow/Underflow and Counter Clearing......................... 347
9.7.18 Contention between TCNT Write and Overflow/Underflow................................ 348
9.7.19 Cautions on Transition from Normal Operation or PWM Mode 1
9.7.20 Output Level in Complementary PWM Mode
9.7.21 Interrupts in Module Standby Mode ..................................................................... 349
9.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection............ 349
MTU2 Output Pin Initialization......................................................................................... 350
9.8.1
9.8.2
9.8.3
9.8.4
10.3.1 Input Level Control/Status Register 1 (ICSR1) .................................................... 387
10.3.2 Output Level Control/Status Register 1 (OCSR1) ................................................ 390
10.3.3 Input Level Control/Status Register 3 (ICSR3) .................................................... 391
Interrupt Signal Timing ........................................................................................ 330
Module Standby Mode Setting ............................................................................. 334
Input Clock Restrictions ....................................................................................... 334
Caution on Period Setting ..................................................................................... 335
Contention between TCNT Write and Clear Operations...................................... 335
Contention between TCNT Write and Increment Operations............................... 336
Contention between TGR Write and Compare Match .......................................... 337
Contention between Buffer Register Write and Compare Match ......................... 338
Contention between Buffer Register Write and TCNT Clear ............................... 339
Contention between TGR Read and Input Capture............................................... 340
to Reset-Synchronized PWM Mode ..................................................................... 348
and Reset-Synchronized PWM Mode................................................................... 349
Operating Modes .................................................................................................. 350
Reset Start Operation ............................................................................................ 350
Operation in Case of Re-Setting Due to Error During Operation, etc. ................. 351
Overview of Initialization Procedures
and Mode Transitions in Case of Error during Operation, etc. ............................. 352