DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 16

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.4 Operation ........................................................................................................................... 444
12.5 SCI Interrupt Sources......................................................................................................... 471
12.6 Serial Port Register (SCSPTR) and SCI Pins .................................................................... 472
12.7 Usage Notes ....................................................................................................................... 473
Section 13 A/D Converter (ADC) .......................................................................477
13.1 Features.............................................................................................................................. 477
13.2 Input/Output Pins............................................................................................................... 479
13.3 Register Descriptions ......................................................................................................... 480
13.4 Operation ........................................................................................................................... 491
13.5 Interrupt Sources................................................................................................................ 497
13.6 Definitions of A/D Conversion Accuracy.......................................................................... 498
13.7 Usage Notes ....................................................................................................................... 501
Rev. 5.00 Mar. 06, 2009 Page xiv of xviii
REJ09B0243-0500
12.4.1 Overview .............................................................................................................. 444
12.4.2 Operation in Asynchronous Mode ........................................................................ 446
12.4.3 Clock Synchronous Mode (Channel 1 in the SH7124 is not Available)............... 456
12.4.4 Multiprocessor Communication Function ............................................................ 465
12.4.5 Multiprocessor Serial Data Transmission ............................................................. 467
12.4.6 Multiprocessor Serial Data Reception .................................................................. 468
12.7.1 SCTDR Writing and TDRE Flag.......................................................................... 473
12.7.2 Multiple Receive Error Occurrence ...................................................................... 473
12.7.3 Break Detection and Processing ........................................................................... 474
12.7.4 Sending a Break Signal......................................................................................... 474
12.7.5 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) ...... 474
12.7.6 Note on Using External Clock in Clock Synchronous Mode................................ 476
12.7.7 Module Standby Mode Setting ............................................................................. 476
13.3.1 A/D Data Registers 0 to 7 (ADDR0 to ADDR7) .................................................. 481
13.3.2 A/D Control/Status Registers_0 and _1 (ADCSR_0 and ADCSR_1) .................. 481
13.3.3 A/D Control Registers_0 and _1 (ADCR_0 and ADCR_1) ................................. 484
13.3.4 A/D Trigger Select Register_0 (ADTSR_0) ......................................................... 487
13.4.1 Single Mode.......................................................................................................... 491
13.4.2 Continuous Scan Mode......................................................................................... 491
13.4.3 Single-Cycle Scan Mode ...................................................................................... 492
13.4.4 Input Sampling and A/D Conversion Time .......................................................... 492
13.4.5 A/D Converter Activation by MTU2 .................................................................... 495
13.4.6 External Trigger Input Timing.............................................................................. 495
13.4.7 2-Channel Scanning.............................................................................................. 496
13.7.1 Module Standby Mode Setting ............................................................................. 501
13.7.2 Permissible Signal Source Impedance .................................................................. 501
13.7.3 Influences on Absolute Accuracy ......................................................................... 501