DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 22

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 1.1
Rev. 5.00 Mar. 06, 2009 Page 2 of 770
REJ09B0243-0500
Items
CPU
Operating modes
User break controller
(UBC)*
On-chip ROM
On-chip RAM
Features
Specification
•
•
•
•
•
•
•
Note:
•
•
•
•
•
•
•
•
•
•
•
•
Central processing unit with an internal 32-bit RISC (Reduced Instruction
Set Computer) architecture
Instruction length: 16-bit fixed length for improved code efficiency
Load-store architecture (basic operations are executed between
registers)
Sixteen 32-bit general registers
Five-stage pipeline
On-chip multiplier: Multiplication operations (32 bits × 32 bits → 64 bits)
executed in two to five cycles
C language-oriented 62 basic instructions
Operating modes
⎯ Single chip mode
Operating states
⎯ Program execution state
⎯ Exception handling state
Power-down modes
⎯ Sleep mode
⎯ Software standby mode
⎯ Module standby mode
Addresses, data values, type of access, and data size can all be set as
break conditions
Supports a sequential break function
Two break channels
128 kbytes (SH71253, SH71243)
64 kbytes (SH71252, SH71242)
32 kbytes (SH71251A, SH71241A)
16 kbytes (SH71250A, SH71240A)
8 kbytes (SH71253, SH71243, SH71252, SH71242, SH71251A,
SH71241A)
4 kbytes (SH71250A, SH71240A)
Some specifications on slot illegal instruction exception handling in
this LSI differ from those of the conventional SH-2. For details, see
section 5.8.4, Notes on Slot Illegal Instruction Exception Handling.