DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 79

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 4 Clock Pulse Generator (CPG)
The clock pulse generator blocks function as follows:
PLL Circuit: The PLL circuit multiples the clock frequency input from the crystal oscillator or
the EXTAL pin by 8. The multiplication ratio is fixed at ×8.
Crystal Oscillator: The crystal oscillator is an oscillator circuit when a crystal resonator is
connected to the XTAL and EXTAL pins.
Divider: The divider generates clocks with the frequencies to be used by the internal clock (Iφ),
bus clock (Bφ), peripheral clock (Pφ), and MTU2 clock (MPφ).
The frequencies can be selected from 1/2, 1/4 (initial value), and 1/8 times the frequency output
from the PLL circuit. The division ratio should be specified in the frequency control register
(FRQCR).
Oscillation Stop Detection Circuit: This circuit detects an abnormal condition in the crystal
oscillator.
Clock Frequency Control Circuit: The clock frequency control circuit controls the clock
frequency according to the setting in the frequency control register (FRQCR).
Standby Control Circuit: The standby control circuit controls the state of the on-chip oscillator
circuit and other modules in sleep or standby mode.
Frequency Control Register (FRQCR): The frequency control register (FRQCR) has control
bits for the frequency division ratios of the internal clock (Iφ), bus clock (Bφ), peripheral clock
(Pφ), and MTU2 clock (MPφ).
Oscillation Stop Detection Control Register (OSCCR): The oscillation stop detection control
register (OSCCR) has an oscillation stop detection flag and a bit for selecting flag status output
through an external pin.
Standby Control Registers 1 to 6 (STBCR1 to STBCR6): The standby control register
(STBCR) has bits for controlling the power-down modes. For details, see section 19, Power-Down
Modes.
Rev. 5.00 Mar. 06, 2009 Page 59 of 770
REJ09B0243-0500