DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 276

MCU RISC FLASH 32K 8K 64LQFP

DF71251AD50FPV

Manufacturer Part Number
DF71251AD50FPV
Description
MCU RISC FLASH 32K 8K 64LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet

Specifications of DF71251AD50FPV

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF71251AD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Example of PWM Mode Setting Procedure: Figure 9.25 shows an example of the PWM mode
setting procedure.
Examples of PWM Mode Operation: Figure 9.26 shows an example of PWM mode 1 operation.
In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA
initial output value and output value, and 1 is set as the TGRB output value.
In this case, the value set in TGRA is used as the period, and the values set in the TGRB registers
are used as the duty levels.
Rev. 5.00 Mar. 06, 2009 Page 256 of 770
REJ09B0243-0500
TGRA
TGRB
H'0000
TIOCA
Select counter clearing
Select counter clock
Select waveform
TCNT value
Set PWM mode
<PWM mode>
Figure 9.25 Example of PWM Mode Setting Procedure
PWM mode
output level
Start count
Set TGR
Figure 9.26 Example of PWM Mode Operation (1)
source
[1]
[2]
[3]
[4]
[5]
[6]
Counter cleared by
TGRA compare match
[1] Select the counter clock with bits TPSC2 to
[2] Use bits CCLR2 to CCLR0 in TCR to select
[3] Use TIOR to designate the TGR as an output
[4] Set the cycle in the TGR selected in [2], and
[5] Select the PWM mode with bits MD3 to MD0
[6] Set the CST bit in TSTR to 1 to start the
TPSC0 in TCR. At the same time, select the
input clock edge with bits CKEG1 and
CKEG0 in TCR.
the TGR to be used as the TCNT clearing
source.
compare register, and select the initial value
and output value.
set the duty in the other TGR.
in TMDR.
count operation.
Time

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