DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 544

MCU RISC FLASH 32K 8K 64LQFP

DF71251AD50FPV

Manufacturer Part Number
DF71251AD50FPV
Description
MCU RISC FLASH 32K 8K 64LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet

Specifications of DF71251AD50FPV

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF71251AD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
15.1.1
PAIORL is a 16-bit readable/writable register that is used to set the pins on port A as inputs or
outputs. Bits PA15IOR to PA0IOR correspond to pins PA15 to PA0 (names of multiplexed pins
are here given as port names and pin numbers alone). PAIORL is enabled when the port A pins are
functioning as general-purpose inputs/outputs (PA15 to PA0). In other states, PAIORL is disabled.
A given pin on port A will be an output pin if the corresponding bit in PAIORL is set to 1, and an
input pin if the bit is cleared to 0.
However, bits 15 to 10, 5, and 2 of PAIORL are disabled in SH7124.
The initial value of PAIORL is H'0000.
Initial value:
15.1.2
PACRL1 to PACRL4 are 16-bit readable/writable registers that are used to select the functions of
the multiplexed pins on port A.
SH7125:
• Port A Control Register L4 (PACRL4)
Initial value:
Rev. 5.00 Mar. 06, 2009 Page 524 of 770
REJ09B0243-0500
Bit
15
R/W:
R/W:
Bit:
Bit:
PA15
R/W
Port A I/O Register L (PAIORL)
IOR
Port A Control Registers L1 to L4 (PACRL1 to PACRL4)
15
15
R
0
0
-
Bit Name
PA14
R/W
PA15
R/W
MD2
IOR
14
14
0
0
PA13
PA15
R/W
R/W
MD1
IOR
13
13
0
0
Initial
Value
0
PA12
R/W
PA15
R/W
MD0
IOR
12
12
0
0
PA11
R/W
IOR
11
11
R
0
0
-
R/W
R
PA10
R/W
PA14
R/W
MD2
IOR
10
10
0
0
R/W
PA14
R/W
MD1
PA9
IOR
9
0
9
0
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W
PA14
R/W
MD0
PA8
IOR
8
0
8
0
R/W
PA7
IOR
R
7
0
7
0
-
R/W
PA13
R/W
MD2
PA6
IOR
6
0
6
0
R/W
PA13
R/W
MD1
PA5
IOR
5
0
5
0
R/W
R/W
PA13
MD0
PA4
IOR
4
0
4
0
R/W
PA3
IOR
R
3
0
3
0
-
R/W
PA12
R/W
MD2
PA2
IOR
2
0
2
0
R/W
PA12
R/W
MD1
PA1
IOR
1
0
1
0
R/W
R/W
PA12
MD0
PA0
IOR
0
0
0
0

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