R4F24268NVRFQV Renesas Electronics America, R4F24268NVRFQV Datasheet - Page 1183
R4F24268NVRFQV
Manufacturer Part Number
R4F24268NVRFQV
Description
MCU 256KB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24268NVZFQV.pdf
(1406 pages)
Specifications of R4F24268NVRFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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H8S/2426, H8S/2426R, H8S/2424 Group
23.2
23.2.1
When bits STC1 and STC0 in PLLCR are set to 11, a transition is made to clock division mode,
and the system clock frequency is divided with respect to the oscillator frequency. Clock division
mode is cancelled by clearing bits STC1 and STC0 to a value other than 11. The timings of
transition and clearing depend on the STCS bit setting in SCKCR. For the operation at transition
and clearing, see section 22.3, System-Clock PLL Circuit and Divider.
If a SLEEP instruction is executed while the SSBY bit in SBYCR is cleared to 0, the chip enters
sleep mode. When sleep mode is cleared by an interrupt, clock division mode is restored.
If a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the chip enters
software standby mode. When software standby mode is cleared by an external or internal
interrupt, clock division mode is restored.
When the RES pin is driven low, the reset state is entered and clock division mode is cleared. The
same applies to a reset caused by watchdog timer overflow.
When the STBY pin is driven low, a transition is made to hardware standby mode.
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
Operation
Clock Division Mode
Section 23 Power-Down Modes
Page 1153 of 1372
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