R4F24268NVRFQV Renesas Electronics America, R4F24268NVRFQV Datasheet - Page 338

MCU 256KB FLASH 48K 144-LQFP

R4F24268NVRFQV

Manufacturer Part Number
R4F24268NVRFQV
Description
MCU 256KB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet

Specifications of R4F24268NVRFQV

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Manufacturer
Quantity
Price
Part Number:
R4F24268NVRFQV
Manufacturer:
Renesas Electronics America
Quantity:
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Part Number:
R4F24268NVRFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 6 Bus Controller (BSC)
Figure 6.97 shows the timing for transition to the bus released state with the synchronous DRAM
interface.
Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424
Page 308 of 1372
Figure 6.97 Bus Release State Transition Timing when Synchronous DRAM Interface
Group.
DQMU, DQML
Precharge-sel
Address bus
SDRAMφ
Data bus
[1] Low level of BREQ signal is sampled at rise of φ.
[2] PALL command is issued.
[3] Bus control signal returns to be high at end of external space access cycle.
[4] BACK signal is driven low, releasing bus to external bus master..
[5] BREQ signal state is also sampled in external bus released state.
[6] High level of BREQ signal is sampled.
[7] BACK signal is driven high, ending external bus release cycle.
[8] When there is external access or refresh request of internal bus master during
[9] BREQO signal goes high 1.5 states after rising edge of BACK signal. If BREQO
BREQO
BREQ
BACK
external bus release while the BREQOE bit is set to 1, BREQO signal goes low.
signal is asserted because of auto-refreshing request, it retains low until auto-refresh cycle starts up.
At least one state from sampling of BREQ signal.
RAS
CAS
CKE
φ
WE
External space read
NOP
T
1
[1]
T
2
[2]
PALL
[3]
address
NOP
Row
[4]
External bus released state
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
[5]
[8]
H8S/2426, H8S/2426R, H8S/2424 Group
[6]
[7]
REJ09B0466-0350 Rev. 3.50
NOP
[9]
CPU
cycle
Jul 09, 2010

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