R4F24268NVRFQV Renesas Electronics America, R4F24268NVRFQV Datasheet - Page 195
R4F24268NVRFQV
Manufacturer Part Number
R4F24268NVRFQV
Description
MCU 256KB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24268NVZFQV.pdf
(1406 pages)
Specifications of R4F24268NVRFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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H8S/2426, H8S/2426R, H8S/2424 Group
6.3.5
CSACRH and CSACRL select whether or not the assertion period of the basic bus interface chip
select signals (CSn) and address signals is to be extended. Extending the assertion period of the
CSn and address signals allows flexible interfacing to external I/O devices.
• CSACRH
• CSACRL
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Bit Name
CSXH7
CSXH6
CSXH5
CSXH4
CSXH3
CSXH2
CSXH1
CSXH0
Bit Name
CSXT7
CSXT6
CSXT5
CSXT4
CSXT3
CSXT2
CSXT1
CSXT0
CS Assertion Period Control Registers H, L (CSACRH, CSACRL)
Initial Value
0
0
0
0
0
0
0
0
Initial Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
CS and Address Signal Assertion Period Control 1
These bits specify whether or not the T
be inserted (see figure 6.3). When an area for
which the CSXHn bit is set to 1 is accessed, a
one-state T
address signals are asserted, is inserted before
the normal access cycle.
0: In area n basic bus interface access, the CSn
1: In area n basic bus interface access, the CSn
Description
CS and Address Signal Assertion Period Control 2
These bits specify whether or not the T
shown in figure 6.3 is to be inserted. When an
area for which the CSXTn bit is set to 1 is
accessed, a one-state T
CSn and address signals are asserted, is inserted
after the normal access cycle.
0: In area n basic bus interface access, the CSn
1: In area n basic bus interface access, the CSn
and address assertion period (T
extended
and address assertion period (T
and address assertion period (T
extended
and address assertion period (T
h
cycle, in which only the CSn and
t
cycle, in which only the
Section 6 Bus Controller (BSC)
h
h
t
t
) is not
) is extended
) is not
) is extended
Page 165 of 1372
h
t
(n = 7 to 0)
(n = 7 to 0)
cycle
cycle is to
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