R4F24268NVRFQV Renesas Electronics America, R4F24268NVRFQV Datasheet - Page 531
R4F24268NVRFQV
Manufacturer Part Number
R4F24268NVRFQV
Description
MCU 256KB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24268NVZFQV.pdf
(1406 pages)
Specifications of R4F24268NVRFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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H8S/2426, H8S/2426R, H8S/2424 Group
9.7
9.7.1
An example is shown in which the DTC is used to receive 128 bytes of data via the SCI.
1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 =
2. Set the start address of the register information at the DTC vector address.
3. Set the corresponding bit in DTCER to 1.
4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the
5. Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an
6. When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have
any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the
SCI RDR address in SAR, the start address of the RAM area where the data will be received in
DAR, and 128 (H'0080) in CRA. CRB can be set to any value.
reception complete (RXI) interrupt. Since the generation of a receive error during the SCI
reception operation will disable subsequent reception, the CPU should be enabled to accept
receive error interrupts.
RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR
to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is
automatically cleared to 0.
DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt
handling routine should perform wrap-up processing.
Examples of Use of the DTC
Normal Mode
Section 9 Data Transfer Controller (DTC)
Page 501 of 1372
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