R4F24268NVRFQV Renesas Electronics America, R4F24268NVRFQV Datasheet - Page 297
R4F24268NVRFQV
Manufacturer Part Number
R4F24268NVRFQV
Description
MCU 256KB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24268NVZFQV.pdf
(1406 pages)
Specifications of R4F24268NVRFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number:
R4F24268NVRFQV
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Renesas Electronics America
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H8S/2426, H8S/2426R, H8S/2424 Group
Section 6 Bus Controller (BSC)
(2)
RAS Down Mode
Even when burst operation is selected, it may happen that access to continuous synchronous
DRAM space is not continuous, but is interrupted by access to another space. In this case, if the
row address active state is held during the access to the other space, the read or write command
can be issued without ACTV command generation similarly to DRAM RAS down mode.
To select RAS down mode, set the BE bit to 1 in DRAMCR regardless of the RCDM bit settings.
The operation corresponding to DRAM RAS up mode is not supported by this LSI.
Figure 6.65 shows an example of the timing in RAS down mode.
Note, however, the next continuous synchronous DRAM space access is a full access if:
• a refresh operation is initiated in the RAS down state
• self-refreshing is performed
• the chip enters software standby mode
• the external bus is released
• the BE bit is cleared to 0
• the mode register of the synchronous DRAM is set
There is synchronous DRAM in which time of the active state of each bank is restricted. If it is not
guaranteed that other row address are accessed in a period in which program execution ensures the
value (software standby, sleep, etc.), auto refresh or self refresh must be set, and the restrictions of
the maximum active state time of each bank must be satisfied. When refresh is not used, programs
must be developed so that the bank is not in the active state for more than the specified time.
REJ09B0466-0350 Rev. 3.50
Page 267 of 1372
Jul 09, 2010
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