MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 120

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Resets and Interrupts
9.3 Maskable interrupts
Technical Data
120
maskable. The remaining sources are maskable, and any one of them
can be given priority over other maskable interrupts.
The priorities of the non-maskable sources are:
Maskable interrupt sources include on-chip peripheral systems and
external interrupt service requests. Interrupts from these sources are
recognized when the global interrupt mask bit (I) in the CCR is cleared.
The default state of the I bit out of reset is one, but it can be written at
any time.
Interrupt sources are prioritized by default but any one maskable
interrupt source may be assigned the highest priority by means of the
HPRIO register. The relative priorities of the other sources remain the
same.
An interrupt that is assigned highest priority is still subject to global
masking by the I bit in the CCR, or by any associated local bits. Interrupt
vectors are not affected by priority assignment. HPRIO can only be
written while the I bit is set (interrupts inhibited).
sources and vectors in default order of priority.
1. POR or RESET pin
2. Clock monitor reset
3. COP watchdog reset
4. Unimplemented instruction trap
5. Software interrupt instruction (SWI)
6. XIRQ signal (if X bit in CCR = 0)
Resets and Interrupts
MC68HC912D60A — Rev. 3.1
Table 9-1
Freescale Semiconductor
lists interrupt