MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 243

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TC6 — Timer Input Capture/Output Compare Register 6
TC7 — Timer Input Capture/Output Compare Register 7
PACTL — 16-Bit Pulse Accumulator A Control Register
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
RESET:
BIT 7
Bit 15
Bit 15
Bit 7
Bit 7
Bit 7
Bit 7
0
0
PAEN
14
14
6
0
6
6
6
6
16-Bit Pulse Accumulator A (PACA) is formed by cascading the 8-bit
pulse accumulators PAC3 and PAC2.
When PAEN is set, the PACA is enabled. The PACA shares the input pin
with IC7.
Read: any time
Write: any time
Depending on the TIOS bit for the corresponding channel, these
registers are used to latch the value of the free-running counter when
a defined transition is sensed by the corresponding input capture
edge detector or to trigger an output action for output compare.
Read anytime. Write anytime for output compare function. Writes to
these registers have no meaning or effect during input capture. All
timer input capture/output compare registers are reset to $0000.
PAMOD
13
13
5
0
5
5
5
5
Enhanced Capture Timer
PEDGE
12
12
4
0
4
4
4
4
CLK1
11
11
3
0
3
3
3
3
CLK0
10
10
2
0
2
2
2
2
PAOVI
1
0
1
9
1
1
9
1
Enhanced Capture Timer
BIT 0
Bit 0
Bit 8
Bit 0
Bit 0
Bit 8
Bit 0
PAI
0
Timer Registers
Technical Data
$009C–$009D
$009E–$009F
$00A0
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