MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 9

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
9.1
9.2
9.3
9.4
9.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Flash EEPROM Control Block . . . . . . . . . . . . . . . . . . . . . . . . . 98
Flash EEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Programming the Flash EEPROM . . . . . . . . . . . . . . . . . . . . . 101
Erasing the Flash EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
EEPROM Selective Write More Zeros . . . . . . . . . . . . . . . . . . 106
EEPROM Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . .107
EEPROM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Program/Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Programming EEDIVH and EEDIVL Registers. . . . . . . . . . . . 116
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Latching of Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Interrupt Control and Priority Registers . . . . . . . . . . . . . . . . . 123
Flash EEPROM Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Flash protection bit FPOPEN . . . . . . . . . . . . . . . . . . . . . . . . . 104
Shadow Word Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Section 9. Resets and Interrupts
Table of Contents
Section 8. EEPROM Memory
Table of Contents
Technical Data
9