MC912D60CCPVE Freescale Semiconductor, MC912D60CCPVE Datasheet - Page 225

• Manufacturer Part Number: MC912D60CCPVE
• Description: IC MCU 16BIT 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60CCPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
M clock
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
Prescaler
÷ 1, 2, ..., 128
Pin logic
Pin logic
Pin logic
Pin logic
Pin logic
Pin logic
Pin logic
Pin logic
Figure 14-1. Timer Block Diagram in Latch Mode
EDG0
EDG1
EDG2
EDG3
EDG5
EDG6
EDG4
EDG7
Delay counter
Delay counter
Delay counter
Delay counter
MUX
MUX
MUX
MUX
16 BIT MAIN TIMER
16-bit Free-running
EDG1
EDG2
EDG3
EDG0
Enhanced Capture Timer
main timer
TC0 capture/compare register
TC1 capture/compare register
TC2 capture/compare register
TC3 capture/compare register
TC4 capture/compare register
TC5 capture/compare register
TC6 capture/compare register
TC7 capture/compare register
M clock
TC1H hold register
TC2H hold register
TC3H hold register
TC0H hold register
Comparator
Comparator
Comparator
Comparator
Comparator
Comparator
Comparator
Comparator
Prescaler
÷ 1, 4, 8, 16
ICLAT, LATQ, BUFEN
to modulus counter
(force latch)
Write $0000
PA0H hold register
PA1H hold register
PA2H hold register
PA3H hold register
PAC0
PAC1
PAC2
PAC3
0
0
0
0
16-bit modulus
down counter
16-bit load register
(MDC latch enable)
RESET
RESET
RESET
RESET
Enhanced Capture Timer
LATQ
Technical Data
Introduction
225