HD6417708RF100A Renesas Electronics America, HD6417708RF100A Datasheet - Page 159

• Manufacturer Part Number: HD6417708RF100A
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708RF100A

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3.15 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

3. Data access cycle break condition setting
4. Instruction fetch cycle break condition setting (example of setting error)
ASID = H'70, after execution of the instruction at address H'00037226 with ASID = H'80.
For channel A, a user break trap occurs when ASID = H'80 and a longword read is performed
at address H'00123454, a word read is performed at address H'00123456, or a byte read is
performed at address H'00123456.
For channel B, a user break trap occurs when ASID = H'70 and H'A512 is written anywhere in
addresses H'000AB000 to H'000ABFFE.
For channel A, a user break trap does not occur since an instruction fetch is not a write cycle.
For channel B, a user break trap does not occur since an instruction fetch is performed on an
even address.
BRCR = H'0080: Independent channel A and B conditions, data break enable
Channel A:
Channel B:
BRCR = H'0000: Independent channel A and B conditions, pre-execution for channel A, pre-
Channel A:
Channel B:
BASRA = H'80:
BARA = H'00123456:
BAMRA = H'00:
BBRA = H'0024:
BASRB = H'70:
BARB = H'000ABCDE: Address H'000ABCDE
BAMRB = H'02:
BBRB = H'002A:
BDRB = H'0000A512:
BDMRB = H'00000000: Data mask H'00000000
execution for channel B
BASRA = H'80:
BARA = H'00027128
BAMRA = H'00:
BBRA = H'001A:
BASRB = H'70:
BARB = H'00031415
BAMRB = H'00:
BBRB = H'0014:
BDRB = H'00000000:
BDMRB = H'00000000: Data mask H'00000000
ASID H'80
Address H'00123456
Address mask H'00
Bus cycle, data access, read (operand size not
included in conditions)
ASID H'70
Address mask H'02
Bus cycle, data access, write, word
Data H'0000A512, (data break enable)
ASID H'80
Address H'00027128
Address mask H'00
Bus cycle, instruction fetch (pre-execution),
write, word
ASID H'70
Address H'00031415
Address mask H'00
Bus cycle, instruction fetch (pre-execution),
read, (operand size not included in conditions)
Data H'00000000
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