HD6417708RF100A Renesas Electronics America, HD6417708RF100A Datasheet - Page 438

• Manufacturer Part Number: HD6417708RF100A
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708RF100A

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3.15 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Switching Modes: When switching from receive mode to transmit mode, check that the receive
operation is completed before starting initialization and setting RE to 0 and TE to 1. The RDRF,
PER, and ORER flags can be used to check if reception is completed. When switching from
transmit mode to receive mode, check that the transmit operation is completed before starting
initialization and setting TE to 0 and RE to 1. The TEND flag can be used to check if transmission
is completed.
Interrupt Operation: In the smart card interface mode, there are three types of interrupts:
transmit-data-empty (TXI), communication error (ERI) and receive-data-full (RXI). In this mode,
the transmit-end interrupt (TEI) cannot be requested.
Set the TEND flag in SCSSR to 1 to request a TXI interrupt. Set the RDRF flag in SCSSR to 1 to
request an RXI interrupt. Set the ORER, PER, or FER/ERS flag in SCSSR to 1 to request an ERI
interrupt (table 14.9).
Table 14.9 Smart Card Mode Operating Status and Interrupt Sources
Mode
Transmit mode
Receive mode
14.4
When the SCI is used as a smart card interface, be sure that all criteria in sections 14.4.1 and
14.4.2 are applied.
14.4.1
In asynchronous mode, the SCI runs on a basic clock with a frequency of 372 times the transfer
rate. During reception, the SCI samples the fall of the start bit using the base clock to achieve
internal synchronization. Receive data is latched internally on the rising edge of the 186th basic
clock cycle (figure 14.8).
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Usage Notes
Receive Data Timing and Receive Margin in Asynchronous Mode
Status
Normal
Error
Normal
Error
Flag
TEND
FER/ERS
RDRF
PER,
ORER
Mask Bit
TIE
RIE
RIE
RIE
Interrupt Source
TXI
ERI
RXI
ERI