HD6417708RF100A Renesas Electronics America, HD6417708RF100A Datasheet - Page 400

• Manufacturer Part Number: HD6417708RF100A
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708RF100A

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3.15 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Figure 13.11 shows SCI transmission with the multiprocessor format.
Receiving Multiprocessor Serial Data: Figure 13.12 shows a sample flowchart for receiving
multiprocessor serial data. The procedure for receiving multiprocessor serial data is:
1. ID receive cycle: Set the MPIE bit in the serial control register (SCSCR) to 1.
2. SCI status check and compare to ID reception: Read the serial status register (SCSSR), check
3. SCI status check and data receiving: Read SCSSR, check that RDRF is set to 1, then read data
4. Receive error handling and break detection: If a receive error occurs, read the ORER and FER
380
TXI interrupt
that RDRF is set to 1, then read data from the receive data register (SCRDR) and compare with
the processor’s own ID. If the ID does not match the receive data, set MPIE to 1 again and
clear RDRF to 0. If the ID matches the receive data, clear RDRF to 0.
from the receive data register (SCRDR).
bits in SCSSR to identify the error. After executing the necessary error handling, clear both
ORER and FER to 0. Receiving cannot resume if ORER or FER remain set to 1. When a
framing error occurs, the RxD pin can be read to detect the break state.
TDRE
TEND
Serial
request
Figure 13.11 SCI Multiprocessor Transmit Operation (Example: 8-Bit Data with
data
1
Start
bit
0
data to TDR and
clears TDRE bit
handler writes
TXI interrupt
D
0
to 0
D
1 frame
Multiprocessor Bit and One Stop Bit)
1
Data
D
processor
7
TXI interrupt
Multi-
request
bit
0/1
Stop
bit
1
Start
bit
0
D
0
D
1
Data
D
processor
7
Multi-
TEI interrupt
bit
0/1
request
Stop
bit
1
(mark)
state
Idle
1