HD6417708RF100A Renesas Electronics America, HD6417708RF100A Datasheet - Page 179

• Manufacturer Part Number: HD6417708RF100A
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708RF100A

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3.15 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

The clock pulse generator blocks function as follows:
1. PLL Circuit 1: PLL circuit 1 doubles, triples*, quadruples, or leaves unchanged the input clock
2. PLL Circuit 2: PLL circuit 2 leaves unchanged or quadruples the frequency of the crystal
EXTAL
Cycle = Bcyc
frequency from the CKIO terminal. The multiplication rate is set by the frequency control
register. When this is done, the phase of the leading edge of the internal clock is controlled so
that it will agree with the phase of the leading edge of the CKIO pin.
oscillator or the input clock frequency coming from the EXTAL pin. The multiplication ratio is
fixed by the clock operation mode. The clock operation mode is set by pins MD0, MD1, and
MD2. See table 9.3 for more information on clock operation modes.
CAP1
CAP2
XTAL
CKIO
MD2
MD1
MD0
FRQCR: Frequency control register
Figure 9.2 Block Diagram of Clock Pulse Generator(SH7708R)
oscillator
Crystal
Clock frequency
control circuit
FRQCR
Clock pulse generator
PLL circuit 1
PLL circuit 2
CPG control unit
( 1, 2, 3,4)
( 1, 4)
Bus interface
Internal bus
Standby control
STBCR
circuit
Divider 2
Divider 1
1
1/2
1/3
1/4
1
1/2
1/3
1/4
Internal
clock (I )
Cycle = Icyc
Peripheral
clock (P )
Cycle = Pcyc
Standby
control
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