HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 101

• Manufacturer Part Number: HD64F3337YCP16V
• Description: MCU 3/5V 60K PB-FREE 84-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16V

• Core Size: 8-Bit
• Program Memory Size: 60KB (60K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• No. Of I/o's: 74
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 6
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PLCC
• Controller Family/series: H8/300
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

4.1
The H8/3337 Series and H8/3397 Series recognize two kinds of exceptions: interrupts and the
reset. Table 4.1 indicates their priority and the timing of their hardware exception-handling
sequence.
Table 4.1
Priority
High
Low
Note: * Not detected after ANDC, ORC, XORC, and LDC instructions.
4.2
4.2.1
A reset has the highest exception-handling priority. When the RES pin goes low or when there is a
watchdog timer reset (when the reset option is selected for watchdog timer overflow), all current
processing stops and the chip enters the reset state. The internal state of the CPU and the registers
of the on-chip supporting modules are initialized. The reset exception-handling sequence starts
when RES returns from low to high, or at the end of a watchdog reset pulse.
4.2.2
The reset state begins when RES goes low or a watchdog reset is generated. To ensure correct
resetting, at power-on the RES pin should be held low for at least 20 ms. In a reset during
operation, the RES pin should be held low for at least 10 system clock cycles. The watchdog reset
pulse width is always 518 system clocks. For the pin states during a reset, see appendix D, Port
States in Each Mode.
Overview
Reset
Overview
Reset Sequence
Type of
Exception
Reset
Interrupt
Hardware Exception-Handling Sequences and Priority
Section 4 Exception Handling
Detection
Timing
Synchronized
with clock
End of instruction
execution*
Timing of Exception-Handling Sequence
The hardware exception-handling sequence begins
as soon as RES changes from low to high.
When an interrupt is requested, the hardware
exception-handling sequence begins at the end of
the current instruction, or at the end of the current
hardware exception-handling sequence.
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