HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 360

• Manufacturer Part Number: HD64F3337YCP16V
• Description: MCU 3/5V 60K PB-FREE 84-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16V

• Core Size: 8-Bit
• Program Memory Size: 60KB (60K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• No. Of I/o's: 74
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 6
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PLCC
• Controller Family/series: H8/300
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

14.4
14.4.1
The host interface can request two types of interrupts to the slave CPU: IBF1 and IBF2. They are
input buffer full interrupts for input data registers IDR1 and IDR2 respectively. Each interrupt is
enabled when the corresponding enable bit is set (table 14.8).
Table 14.8 Input Buffer Full Interrupts
Interrupt
IBF1
IBF2
14.4.2
In slave mode (when HIE = 1 in SYSCR in single-chip mode), three bits in the port 4 data register
(P4DR) can be used as host interrupt request latches.
These three P4DR bits are cleared to 0 by the host processor’s read signal (IOR). If CS
are low, when IOR goes low and the host reads ODR1, HIRQ
and HA
generate a host interrupt request, normally on-chip software writes 1 to the corresponding bit. In
processing the interrupt, the host’s interrupt-handling routine reads the output data register (ODR1
or ODR2), and this clears the host interrupt latch to 0.
Table 14.9 indicates how these bits are set and cleared. Figure 14.3 shows the processing in
flowchart form.
Table 14.9 Host Interrupt Signal Set/Clear Conditions
Host Interrupt
Signal
HIRQ
HIRQ
HIRQ
330
11
1
12
(P4
(P4
(P4
0
are low, when IOR goes low and the host reads ODR2, HIRQ
Interrupts
IBF1, IBF2
HIRQ
4
3
)
5
)
)
11
Description
Requested when IBFIE1 is set to 1 and IDR1 is full
Requested when IBFIE2 is set to 1 and IDR2 is full
, HIRQ
Setting Condition
Slave CPU reads 0 from P4DR bit 3,
then writes 1
Slave CPU reads 0 from P4DR bit 4,
then writes 1
Slave CPU reads 0 from P4DR bit 5,
then writes 1
1
, and HIRQ
12
Clearing Condition
Slave CPU writes 0 in P4DR bit 3, or
host reads output data register 2
Slave CPU writes 0 in P4DR bit 4, or
host reads output data register 1
Slave CPU writes 0 in P4DR bit 5, or
host reads output data register 1
1
and HIRQ
11
is cleared to 0. To
12
are cleared to 0. If CS
1
and HA
0
2