HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 339
HD64F3337YCP16V
Manufacturer Part Number
HD64F3337YCP16V
Description
MCU 3/5V 60K PB-FREE 84-PLCC
Manufacturer
Renesas Electronics America
Series
H8® H8/300r
Specifications of HD64F3337YCP16V
Core Size
8-Bit
Program Memory Size
60KB (60K x 8)
Oscillator Type
Internal
Core Processor
H8/300
Speed
16MHz
Connectivity
Host Interface, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Operating Temperature
-20°C ~ 75°C
Package / Case
84-PLCC
No. Of I/o's
74
Ram Memory Size
1KB
Cpu Speed
16MHz
No. Of Timers
6
No. Of Pwm Channels
2
Digital Ic Case Style
PLCC
Controller Family/series
H8/300
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F3337YCP16V
Manufacturer:
COILMASTER
Quantity:
30 000
Company:
Part Number:
HD64F3337YCP16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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13.4
1. In master mode, if an instruction to generate a start condition is immediately followed by an
2. Either of the following two conditions will start the next transfer. Pay attention to these
3. The I
CKDBL
0
0
1
1
4. Note on Issuance of Retransmission Start Condition
instruction to generate a stop condition, neither condition will be output correctly. To output
consecutive start and stop conditions, after issuing the instruction that generates the start
condition, read the relevant ports, check that SCL and SDA are both low, then issue the
instruction that generates the stop condition.
conditions when reading or writing to ICDR.
speed mode). In master mode, the I
one bit at a time during communication. If tsr (the time for SCL to go from low to V
the time determined by the input clock of the I
extended. SCL rise time is determined by the pull-up resistance and load capacitance of the
SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance and
load capacitance so that the SCL rise time falls below the values given in the table below.
When issuing a retransmission start condition, the condition must be issued after the SCL clock
falls during the acknowledge bit reception period. After the end of the acknowledge bit, the
next data should be written to ICDR after SCL goes high. Figure 13.16 shows the
recommended program flow for issuing a retransmission start condition. A timing chart for the
flowchart in figure 13.16 is shown in figure 13.17.
Write access to ICDR when ICE = 1 and TRS = 1
Read access to ICDR when ICE = 1 and TRS = 0
2
C bus interface specification for the SCL rise time tsr is under 1000 ns (300 ns for high-
Application Notes
IICX
0
1
0
1
t
Display
7.5t
17.5t
37.5t
cyc
cyc
cyc
cyc
Normal
mode
High-speed
mode
Normal
mode
High-speed
mode
Normal
mode
High-speed
mode
2
C bus interface monitors the SCL line and synchronizes
ø = 5 MHz
1000 ns
300 ns
1000 ns
300 ns
1000 ns
300 ns
2
C bus interface, the high period of SCL is
Time Display
ø = 8 MHz
937 ns
300 ns
1000 ns
300 ns
1000 ns
300 ns
ø = 10 MHz ø = 16 MHz
750 ns
300 ns
1000 ns
300 ns
1000 ns
300 ns
486 ns
300 ns
1000 ns
300 ns
1000 ns
300 ns
IH
) exceeds
309
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