HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 476
HD64F3337YCP16V
Manufacturer Part Number
HD64F3337YCP16V
Description
MCU 3/5V 60K PB-FREE 84-PLCC
Manufacturer
Renesas Electronics America
Series
H8® H8/300r
Specifications of HD64F3337YCP16V
Core Size
8-Bit
Program Memory Size
60KB (60K x 8)
Oscillator Type
Internal
Core Processor
H8/300
Speed
16MHz
Connectivity
Host Interface, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Operating Temperature
-20°C ~ 75°C
Package / Case
84-PLCC
No. Of I/o's
74
Ram Memory Size
1KB
Cpu Speed
16MHz
No. Of Timers
6
No. Of Pwm Channels
2
Digital Ic Case Style
PLCC
Controller Family/series
H8/300
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F3337YCP16V
Manufacturer:
COILMASTER
Quantity:
30 000
Company:
Part Number:
HD64F3337YCP16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Automatic Alignment of SCI Bit Rate
When started in boot mode, the H8/3337YF measures the low period in asynchronous SCI data
transmitted from the host (figure 20.5). The data format is eight data bits, one stop bit, and no
parity bit. From the measured low period (9 bits), the H8/3337YF computes the host’s bit rate.
After aligning its own bit rate, the H8/3337YF sends the host 1 byte of H'00 data to indicate that
bit-rate alignment is completed. The host should check that this alignment-completed indication is
received normally and send one byte of H'55 back to the H8/3337YF. If the alignment-completed
indication is not received normally, the H8/3337YF should be reset, then restarted in boot mode to
measure the low period again. There may be some alignment error between the host’s and
H8/3337YF’s bit rates, depending on the host’s bit rate and the H8/3337YF’s system clock
frequency. To have the SCI operate normally, set the host’s bit rate to 2400, 4800, or 9600 bps
Table 20.8 lists typical host bit rates and indicates the clock-frequency ranges over which the
H8/3337YF can align its bit rate automatically. Boot mode should be used within these frequency
ranges
Table 20.8 System Clock Frequencies Permitting Automatic Bit-Rate Alignment by
Host Bit Rate
9600 bps
4800 bps
2400 bps
Notes: *1 Use a host bit rate setting of 2400, 4800, or 9600 bps only. No other setting should be
446
*2
.
*2 Although the H8/3337YF may also perform automatic bit-rate alignment with bit rate
Figure 20.5 Measurement of Low Period in Data Transmitted from Host
used.
and system clock combinations other than those shown in table 20.8, there will be a
slight difference between the bit rates of the host and the H8/3337YF, and subsequent
transfer will not be performed normally. Therefore, only a combination of bit rate and
system clock frequency within one of the ranges shown in table 20.8 can be used for
boot mode execution.
H8/3337YF
*1
Start
bit
D0
This low period (9 bits) is measured (H'00 data)
System Clock Frequencies Permitting Automatic Bit-Rate Alignment
by H8/3337YF
8 MHz to 16 MHz
4 MHz to 16 MHz
2 MHz to 16 MHz
D1
D2
D3
D4
D5
D6
D7
Stop
bit
High for at
least 1 bit
*1
.
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