HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 322
HD64F3337YCP16V
Manufacturer Part Number
HD64F3337YCP16V
Description
MCU 3/5V 60K PB-FREE 84-PLCC
Manufacturer
Renesas Electronics America
Series
H8® H8/300r
Specifications of HD64F3337YCP16V
Core Size
8-Bit
Program Memory Size
60KB (60K x 8)
Oscillator Type
Internal
Core Processor
H8/300
Speed
16MHz
Connectivity
Host Interface, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Operating Temperature
-20°C ~ 75°C
Package / Case
84-PLCC
No. Of I/o's
74
Ram Memory Size
1KB
Cpu Speed
16MHz
No. Of Timers
6
No. Of Pwm Channels
2
Digital Ic Case Style
PLCC
Controller Family/series
H8/300
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F3337YCP16V
Manufacturer:
COILMASTER
Quantity:
30 000
Company:
Part Number:
HD64F3337YCP16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bit 3—Arbitration Lost Flag (AL): This flag indicates that arbitration was lost in master mode.
The I
at nearly the same time, if the I
AL to 1 to indicate that the bus has been taken by another master. At the same time, it sets the
IRIC bit in ICSR to generate an interrupt request.
AL is cleared by reading AL after it has been set to 1, then writing 0 in AL. In addition, AL is
reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
Bit 3: AL
0
1
Bit 2—Slave Address Recognition Flag (AAS): When the addressing format is selected (FS = 0)
in slave receive mode, this flag is set to 1 if the first byte following a start condition matches bits
SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected.
AAS is cleared by reading AAS after it has been set to 1, then writing 0 in AAS. In addition, AAS
is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
Bit 2: AAS
0
1
292
2
C bus interface monitors the bus. When two or more master devices attempt to seize the bus
Description
Bus arbitration won
This bit is cleared to 0 at the following times:
Arbitration lost
This bit is set to 1 at the following times:
Description
Slave address or general call address not recognized
This bit is cleared to 0 at the following times:
Slave address or general call address recognized
This bit is set to 1 at the following times:
When ICDR data is written (transmit mode) or read (receive mode)
When AL is read while AL = 1, then 0 is written in AL
If the internal SDA signal and bus line disagree at the rise of SCL in master
transmit mode
If the internal SCL is high at the fall of SCL in master transmit mode
When ICDR data is written (transmit mode) or read (receive mode)
When AAS is read while AAS = 1, then 0 is written in AAS
When the slave address or general call address is detected in slave receive
mode
2
C bus interface detects data differing from the data it sent, it sets
(Initial value)
(Initial value)
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