HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 312

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 7 Instruction Set
Table 7.10 Floating-Point Double-Precision Instructions
Instruction
FABS
FADD
FCMP/EQ
FCMP/GT
FDIV
FCNVDS
FCNVSD
FLOAT
FMUL
FNEG
FSQRT
FSUB
FTRC
Table 7.11 Floating-Point Control Instructions
Instruction
LDS
LDS
LDS.L
LDS.L
STS
STS
STS.L
STS.L
Rev.7.00 Oct. 10, 2008 Page 226 of 1074
REJ09B0366-0700
Rm,FPSCR
Rm,FPUL
@Rm+,FPSCR
@Rm+,FPUL
FPSCR,Rn
FPUL,Rn
FPSCR,@-Rn
FPUL,@-Rn
DRn
DRm,DRn
DRm,DRn
DRm,DRn
DRm,DRn
DRm,FPUL
FPUL,DRn
FPUL,DRn
DRm,DRn
DRn
DRn
DRm,DRn
DRm,FPUL
Operation
DRn & H'7FFF FFFF FFFF FFFF
→ DRn
DRn + DRm → DRn
When DRn = DRm, 1 → T
Otherwise, 0 → T
When DRn > DRm, 1 → T
Otherwise, 0 → T
DRn /DRm → DRn
double_to_ float[DRm] → FPUL 1111mmm010111101 —
float_to_ double [FPUL] → DRn 1111nnn010101101 —
(float)FPUL → DRn
DRn * DRm → DRn
DRn ^ H'8000 0000 0000 0000
→ DRn
DRn – DRm → DRn
(long) DRm → FPUL
Operation
Rm → FPSCR
Rm → FPUL
(Rm) → FPSCR, Rm+4 → Rm
(Rm) → FPUL, Rm+4 → Rm
FPSCR → Rn
FPUL → Rn
Rn – 4 → Rn, FPSCR → (Rn)
Rn – 4 → Rn, FPUL → (Rn)
DRn → DRn
Instruction Code
1111nnn001011101 —
1111nnn0mmm00000 —
1111nnn0mmm00100 —
1111nnn0mmm00101 —
1111nnn0mmm00011 —
1111nnn000101101 —
1111nnn0mmm00010 —
1111nnn001001101 —
1111nnn001101101 —
1111nnn0mmm00001 —
1111mmm000111101 —
Instruction Code
0100mmmm01101010 —
0100mmmm01011010 —
0100mmmm01100110 —
0100mmmm01010110 —
0000nnnn01101010 —
0000nnnn01011010 —
0100nnnn01100010 —
0100nnnn01010010 —
Privileged
Privileged
T Bit
—
—
Comparison
result
Comparison
result
—
—
—
—
—
—
—
—
—
T Bit
—
—
—
—
—
—
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