HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 739

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

7. When falling edge detection is used for external requests, keep the external request pin high
8. When using the DMAC in single address mode, set an external address as the address. All
9. In external request (DREQ) edge detection in the SH7750R, an external request that has been
10. SH7750 Only: When a DMA transfer is performed between an on-chip peripheral module and
when making DMAC settings.
channels will halt due to an address error if an on-chip peripheral module address is set.
accepted can be cancelled in the following way. Firstly, negate DREQ and change the value of
CHCR.DS from 1 to 0. After that, set the CHCR.DS bit back to 1, then assert DREQ. (Though
the SH7750R does not have a DMAOR.COD bit, similar to when the DMAOR.COD bit is 1 in
the SH7750S, external requests that have once been accepted can be cancelled when the
external request (DREQ) edge is detected.)
external memory, the data may not be transferred correctly if the following conditions apply.
To work around this problem, use the CPU to transfer the data.
⎯ Conditions Under which Problem Occurs
⎯ Description of Problem
Notes: 1. The registers corresponding to the above conditions are the following.
a. Big endian is selected.
b. The external memory bus width is 32 bits.
c. Data is being transferred from an on-chip peripheral module*
d. The transmit size*
Conditions a. to d. must all be satisfied.
When transferring data from an on-chip peripheral module, bits 15 to 8 of the 32-bit data
become misaligned. As a result, the data is not transferred correctly.
Data that should be transferred:
Data actually transferred to external memory: 12 34 12 78
2. Set by the transmit size bits in the DMA channel control register.
TMU.TCOR0
TMU.TCNT0
TMU.TCOR1
TMU.TCNT1
TMU.TCOR2
TMU.TCNT2
TMU.TCPR2
H-UDI.SDDR
2
of the data to be transferred is 32 bits.
Section 14 Direct Memory Access Controller (DMAC)
12 34 56 78
Rev.7.00 Oct. 10, 2008 Page 653 of 1074
1
to external memory.
REJ09B0366-0700